LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY msecond IS
PORT( rst,st_ps,clk,rci1:IN STD_LOGIC;
cout1:OUT STD_LOGIC;
out1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END msecond;
ARCHITECTURE behav OF msecond IS
BEGIN
PROCESS(rst,st_ps,clk,rci1)
VARIABLE xch1:STD_LOGIC;
VARIABLE xch2:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
IF rst='1' THEN xch2:="0000000";
ELSIF clk'EVENT AND clk='1' THEN
IF st_ps='1' THEN
IF xch2="1100011" THEN
xch2:="0000000";
xch1:='1';
ELSE
xch2:=xch2+1;
END IF;
END IF;
END IF;
IF rci1='1' THEN xch1:='0';
END IF;
cout1<=xch1;
out1<=xch2;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY second IS
PORT( rst,st_ps,cin2,rci2:IN STD_LOGIC;
cout2,rco2:OUT STD_LOGIC;
out2:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END second;
ARCHITECTURE behav OF second IS
BEGIN
PROCESS(rst,st_ps,cin2,rci2)
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