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S905D-DVB-Readme
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更新于2023-03-16
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在S905D上增加DVB模块的指导文档,主要包括DVB驱动的选择和配置,DVB功能的开关还有相关的配置方法
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S905D
Datasheet
Revision: 0.6
Release date: 8/1/2017
Amlogic, Ltd.
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S905D Datasheet
Revision 0.6
AMLOGIC, Inc. Proprietary
2/555
COPYRIGHT
© 2017 Amlogic, Ltd.
All rights reserved. No part of this document may be reproduced. Transmitted, transcribed, or translated into any language in
any form or by any means with the written permission of Amlogic, Ltd.
TRADEMARKS
AMLOGIC is a trademark of Amlogic, Ltd. All other trademarks and registered trademarks are property of their respective
companies.
DISCLAIMER
Amlogic Ltd. may make improvements and/or changes in this document or in the product described in this document at any
time.
This product is not intended for use in medical, life saving, or life sustaining applications.
Circuit diagrams and other information relating to products of Amlogic Ltd. are included as a means or illustrating typical
applications. Consequently, complete information sufficient for production design is not necessarily given. Amlogic makes no
representations or warranties with respect to the accuracy or completeness of the contents presented in this document.
REVISION HISTORY
Revision
Number
Revision Date
Changes
0.1
2016/10/21
Initial version release
0.2
2016/12/05
Add TSin timing information, blkmv update to ACODEC, delete BT656_2
information, update GPIO information, update power on sequence information,
update pcmin_ctrl1 register bit [26:21][20:16] description
0.3
2017/3/14
Add register RESET0_MASK~RESET7_MASK, change RESET0_LEVEL ~RESET7_LEVEL
address to 0xc11004480~ 0xc1100449c
0.4
2017/6/2
Update A53 CIG bit to IRQ num in TableIII.23.1
0.5
2017/7/12
Update Ethernet PHY feature
0.6
2017/8/1
Update Ethernet Mac register information
CONTACT INFORMATION
Amlogic, Shanghai, Ltd.
2518 Mission College Blvd, Suite 120
Santa Clara, CA 95054
U.S.A.
www.amlogic.com
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S905D Datasheet
Revision 0.6
AMLOGIC, Inc. Proprietary
3/555
Contents
Section I About This Documentation ........................................................................................................................ 8
1. Documentation Overview .................................................................................................................................. 8
2. Acronyms and Abbreviations ............................................................................................................................. 9
Section II General Information ............................................................................................................................. 10
3. Features ........................................................................................................................................................... 11
3.1 CPU Architecture ...................................................................................................................................... 11
3.2 GPU Architecture ...................................................................................................................................... 11
3.3 Crypto Engine ........................................................................................................................................... 11
3.4 Video Path ................................................................................................................................................ 11
3.5 Audio Path ................................................................................................................................................ 12
3.6 Memory .................................................................................................................................................... 12
3.7 Digital Television Interface ....................................................................................................................... 12
3.8 I/O Interfaces ............................................................................................................................................ 12
3.9 System Interface ....................................................................................................................................... 12
3.10 Power Management ............................................................................................................................. 12
3.11 Security ................................................................................................................................................. 13
4. System Block Diagram ..................................................................................................................................... 14
5. Pin-Out Diagram (Top view) ......................................................................................................................... 15
6. Pin Description ................................................................................................................................................. 16
7. Pin Multiplexing ............................................................................................................................................... 27
8. Signal Description ............................................................................................................................................ 31
9. Absolute Maximum Ratings ............................................................................................................................. 37
10. Recommended Operating Conditions .......................................................................................................... 38
11. Thermal Operating Specifications ................................................................................................................ 39
12. DC Electrical Characteristics ......................................................................................................................... 40
12.1 Normal GPIO Specifications .................................................................................................................. 40
12.2 Open Drain GPIO Specifications ............................................................................................................ 40
12.3 DDR3/DDR3L/DDR4/LPDDR2/LPDDR3 SDRAM Specifications ............................................................ 40
12.4 Recommended Oscillator Electrical Characteristics ............................................................................. 41
13. Recommended Power on sequence ............................................................................................................ 43
14. Power Consumption ..................................................................................................................................... 44
15. Mechanical Dimension ................................................................................................................................. 45
Section III System ................................................................................................................................................... 47
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16. Memory Map ............................................................................................................................................... 48
17. Power Domain .............................................................................................................................................. 51
17.1 Top Level Power Domains..................................................................................................................... 52
17.2 A53 Power Modes ................................................................................................................................. 52
17.3 EE Top Level Power Modes ................................................................................................................... 53
17.4 Mali Power Modes ................................................................................................................................ 53
17.5 Power/Isolation/Memory Power Down Register Summary ................................................................. 54
18. System Booting ............................................................................................................................................ 57
18.1 Overview ............................................................................................................................................... 57
18.2 Power-on Flow Chart ............................................................................................................................ 57
19. CPU ............................................................................................................................................................... 58
19.1 Overview ............................................................................................................................................... 58
20. GPU .............................................................................................................................................................. 59
21. Clock and Reset ............................................................................................................................................ 60
21.1 Overview ............................................................................................................................................... 60
21.2 Clock Trees ............................................................................................................................................ 60
21.3 Clock Gating .......................................................................................................................................... 66
21.4 Register Description .............................................................................................................................. 70
22. GPIO ............................................................................................................................................................. 96
22.1 Overview ............................................................................................................................................... 96
22.2 GPIO Multiplex Function ....................................................................................................................... 96
22.3 GPIO Interrupt .................................................................................................................................... 101
22.4 Register Description ............................................................................................................................ 102
23. Interrupt Control ........................................................................................................................................ 105
23.1 Overview ............................................................................................................................................. 105
23.2 Interrupt Source .................................................................................................................................. 105
23.3 Register Description ............................................................................................................................ 108
24. TIMER ......................................................................................................................................................... 111
24.1 Overview ............................................................................................................................................. 111
24.2 General-Purpose Timer ....................................................................................................................... 111
24.3 Watchdog Timer ................................................................................................................................. 111
24.4 Register Definitions ............................................................................................................................. 112
25. Crypto ......................................................................................................................................................... 117
25.1 Overview ............................................................................................................................................. 117
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25.2 Key Ladder .......................................................................................................................................... 117
25.3 RNG ..................................................................................................................................................... 117
25.4 EFUSE .................................................................................................................................................. 117
Section IV Video Path ........................................................................................................................................... 118
26. Video Input ................................................................................................................................................. 119
26.1 Overview ............................................................................................................................................. 119
26.2 TSin Timing .......................................................................................................................................... 119
26.3 Demux ................................................................................................................................................. 120
26.4 Register Definition .............................................................................................................................. 120
27. Video Output .............................................................................................................................................. 134
27.1 Overview ............................................................................................................................................. 134
27.2 VPU ..................................................................................................................................................... 134
27.3 RDMA .................................................................................................................................................. 343
27.4 HDMI ................................................................................................................................................... 350
27.5 CVBS and LCD ...................................................................................................................................... 358
Section V Audio Path .......................................................................................................................................... 402
28. Audio_Input ............................................................................................................................................... 403
28.1 Overview ............................................................................................................................................. 403
28.2 SPDIF ................................................................................................................................................... 403
28.3 I2S(decode) ......................................................................................................................................... 403
28.4 PCM(decode) ...................................................................................................................................... 404
28.5 PDM .................................................................................................................................................... 405
28.6 To_ddr ................................................................................................................................................. 405
28.7 Register Description ............................................................................................................................ 407
29. Audio Output .............................................................................................................................................. 421
29.1 Overview ............................................................................................................................................. 421
29.2 SPDIF(encode) ..................................................................................................................................... 421
29.3 I2S(encode) ......................................................................................................................................... 422
29.4 Audio Codec ........................................................................................................................................ 424
29.5 Register Description ............................................................................................................................ 424
Section VI Memory INTERFACE ............................................................................................................................ 443
30. DDR ............................................................................................................................................................ 444
30.1 Overview ............................................................................................................................................. 444
30.2 Register Description ............................................................................................................................ 444
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