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ARM Architecture Reference Manual.pdf
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ARM Architecture Reference Manual.pdf
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ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM Architecture
Reference Manual
ii
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
Copyright © 1996–2000 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this document.
Proprietary Notice
ARM, the ARM Powered logo, Thumb, and StrongARM are registered trademarks of ARM Limited.
The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, PrimeCell, ARM7TDMI,
ARM7TDMI-S, ARM9TDMI, ARM9E-S, ETM7, ETM9, TDMI, STRONG, are trademarks of ARM Limited.
All other products or services mentioned herein may be trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted
or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss
or damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
Change History
Date Issue Change
February 1996 A First edition.
July 1997 B Updated and index added.
April 1998 C Updated.
February 2000 D Updated for ARM architecture v5.
June 2000 E Updated for ARM architecture v5TE and
corrections to Part B.
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
iii
Preface
This preface describes the versions of the ARM architecture and the contents of this manual, then lists the
conventions and terminology it uses.
• About this manual on page iv
• Architecture versions and variants on page v
• Using this manual on page x
• Conventions on page xii.
Preface
iv
Copyright © 1996-2000 ARM Limited. All rights reserved.
ARM DDI 0100E
About this manual
The purpose of this manual is to describe the ARM instruction set architecture, including its high code
density Thumb subset, and two of its standard coprocessor extensions:
• The standard System Control coprocessor (coprocessor 15), which is used to control memory system
components such as caches, write buffers, Memory Management Units, and Protection Units.
•The Vector Floating-point (VFP) architecture, which uses coprocessors 10 and 11 to supply a
high-performance floating-point instruction set.
These instruction sets are described primarily from the viewpoint of the instruction being a 32-bit word or
16-bit halfword. The precise effects of each instruction are described, including any restrictions on its use.
This information is of primary importance to authors of compilers, assemblers, and other programs that
generate ARM machine code.
Assembler syntax is given for most of the instructions described in this manual, allowing instructions to be
specified in textual form. This is of considerable use to assembly code writers, and also when debugging
either assembler or high-level language code at the single instruction level.
However, this manual is not intended as tutorial material for ARM assembler language, nor does it describe
ARM assembler language at anything other than a very basic level. To make effective use of ARM
assembler language, consult the documentation supplied with the assembler being used. Different
assemblers vary considerably with respect to many aspects of assembler language, such as which assembler
directives are accepted and how they are coded.
A considerable amount of generic information is also included about how ARM processors access memory
and other system components. Although this usually needs to be supplemented by detailed
implementation-specific information from the technical reference manual of the device being used, this
information is of use to designers of ARM-based systems.
Preface
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
v
Architecture versions and variants
The ARM instruction set architecture has evolved significantly since it was first developed, and will
continue to be developed in the future. In order to be precise about which instructions exist in any particular
ARM implementation, five major versions of the instruction set have been defined to date. These are
denoted by the version numbers 1 to 5.
Many of the versions can be qualified with variant letters to specify collections of additional instructions
that are included in that version. These collections vary from being very small (the M variant denotes the
addition of just four extra instructions) to very large (the T variant denotes the addition of the entire Thumb
instruction set).
The five versions of the ARM instruction set architecture to date are as follows:
Version 1 This version was implemented only by ARM1, and was never used in a commercial product.
It contained:
• the basic data-processing instructions (not including multiplies)
• byte, word, and multi-word load/store instructions
• branch instructions, including a branch-and-link instruction designed for subroutine
calls
• a software interrupt instruction, for use in making Operating System calls.
Version 1 only had a 26-bit address space, and is now obsolete.
Version 2 This version extended architecture version 1 by adding:
• multiply and multiply-accumulate instructions
• coprocessor support
• two more banked registers in fast interrupt mode
• atomic load-and-store instructions called SWP and SWPB (in a slightly later variant
called version 2a).
Versions 2 and 2a still only had a 26-bit address space, and are now obsolete.
Version 3 This architecture version extended the addressing range to 32 bits. Program status
information which had previously been stored in R15 was moved to a new Current Program
Status Register (CPSR), and Saved Program Status Registers (SPSRs) were added to
preserve the CPSR contents when an exception occurred. As a result, the following changes
occurred to the instruction set:
• two instructions (MRS and MSR) were added to allow the new CPSR and SPSRs to be
accessed.
• the functionality of instructions previously used to return from exceptions was
modified to allow them to continue to be used for that purpose.
Version 3 also added two new processor modes in order to make it possible to use Data
Abort, Prefetch Abort and Undefined Instruction exceptions effectively in Operating
System code.
Backwards-compatibility support for the 26-bit architectures was obligatory in version 3,
except in a variant called version 3G. The distinction between versions 3 and 3G is now
obsolete.
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