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IEEE SystemVerilog Standard 1800-2012
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数字集成电路编程语言SystemVerilog标准,IEEE 1800-2012属于公开资料。可读性非常强,适合从事IC验证与设计的人学习之。
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IEEE Standard for SystemVerilog—
Unified Hardware Design, Specification, and
Ve
rification Language
Sponsored by the
Design Automation Standards Committee
IEEE
3 Park Avenue
New York, NY 10016-5997
USA
21 February 2013
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group
IEEE Std 1800™-2012
(Revision of
IEEE Std 1800-2009)
Authorized licensed use limited to: CADENCE DESIGN SYSTEMS. Downloaded on June 24,2013 at 08:36:32 UTC from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: CADENCE DESIGN SYSTEMS. Downloaded on June 24,2013 at 08:36:32 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800™-2012
(Revision of
IEEE Std 1800-2009)
IEEE Standard for SystemVerilog—
Unified Hardware Design, Specification, and
Verification Language
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group
Approved 5 December 2012
IEEE-SA Standards Board
Authorized licensed use limited to: CADENCE DESIGN SYSTEMS. Downloaded on June 24,2013 at 08:36:32 UTC from IEEE Xplore. Restrictions apply.
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2013 by The Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 21 February 2013. Printed in the United States of America.
IEEE, 802, and POSIX are registered trademarks in the U.S. Patent & Trademark Office, owned by The Institute of
Electrical and Electronics Engineers, Incorporated.
Verilog is a registered trademark of Cadence Design Systems, Inc.
P'): ISBN 978-0-7381-811
-67'GT
PULQW:ISBN 978-0-7381-811-STDPD98078
IEEE prohibits discrimination, harassment and bullying. For more information, visit http://www.ieee.org/web/aboutus/whatis/policies/p9-26.html.
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Abstract: The definition of the language syntax and semantics for SystemVerilog, which is a unified
hardware design, specification, and verification language, is provided. This standard includes
support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level
abstraction levels, and for writing testbenches using coverage, assertions, object-oriented
programming, and constrained random verification. The standard also provides application
programming interfaces (APIs) to foreign programming languages.
Keywords: assertions, design automation, design verification, hardware description language,
HDL, HDVL, IEEE 1800
™, PLI, programming language interface, SystemVerilog, Verilog
®
, VPI
Authorized licensed use limited to: CADENCE DESIGN SYSTEMS. Downloaded on June 24,2013 at 08:36:32 UTC from IEEE Xplore. Restrictions apply.
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Authorized licensed use limited to: CADENCE DESIGN SYSTEMS. Downloaded on June 24,2013 at 08:36:32 UTC from IEEE Xplore. Restrictions apply.
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