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1. General Description 2. Features 3. Block Diagram 4. Pin Assignments 5. Physical Layer Function Description 6. Switch Core Function Description 7. Interface Descriptions 8. LDO Regulator 9. Electrical Characteristics 10. Mechanical Dimensions 11. Ordering Information
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RTL8309N
SINGLE-CHIP 8-PORT 10/100MBPS
ETHERNET SWITCH CONTROLLER
DATASHEET
Draft
Rev. 1.0
10 January 2012
Track ID:
9-Port 10/100Mbps Ethernet Switch Controller i Track ID: Rev. 1.0
RTL8309N
Datasheet
COPYRIGHT
©2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
CONFIDENTIALITY
This document is confidential and should not be provided to a third-party without the permission of
Realtek Semiconductor Corporation.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date
Summary
1.0 2012-1-10 First release.
8-Port 10/100Mbps Ethernet Switch Controller ii Track ID: Rev. 1.0
RTL8309N
Datasheet
Contents
1. GENERAL DESCRIPTION................................................................................................................................................0
2. FEATURES...........................................................................................................................................................................1
3. BLOCK DIAGRAM.............................................................................................................................................................3
4. PIN ASSIGNMENTS...........................................................................................................................................................4
4.1. PIN ASSIGNMENTS DIAGRAM .......................................................................................................................................4
4.2. PACKAGE IDENTIFICATION ...........................................................................................................................................5
4.3. PIN ASSIGNMENTS TABLE ............................................................................................................................................5
4.4. PIN DESCRIPTIONS .......................................................................................................................................................1
4.4.1. Media Connection Pins......................................................................................................................................1
4.4.2. Parallel LED Pins..............................................................................................................................................1
4.4.3. Miscellaneous Interface Pins.............................................................................................................................2
4.4.4. Configuration Strapping Pins............................................................................................................................2
4.4.5. Regulator Pins ...................................................................................................................................................3
4.4.6. Power and GND Pins ........................................................................................................................................4
5. PHYSICAL LAYER FUNCTION DESCRIPTION ..........................................................................................................4
5.1. MDI INTERFACE...........................................................................................................................................................4
5.2. 10BASE-T TRANSMIT FUNCTION..................................................................................................................................5
5.3. 10BASE-T RECEIVE FUNCTION ....................................................................................................................................5
5.4. 100BASE-TX TRANSMIT FUNCTION.............................................................................................................................5
5.5. 100BASE-TX RECEIVE FUNCTION ...............................................................................................................................5
5.6. 100BASE-FX FUNCTION ..............................................................................................................................................5
5.7. AUTO-NEGOTIATION FOR UTP FUNCTION....................................................................................................................6
5.8. CROSSOVER DETECTION AND AUTO CORRECTION FUNCTION......................................................................................6
5.9. POLARITY CORRECTION FUNCTION..............................................................................................................................6
5.10. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET FUNCTION (EEE) .................................................................................6
5.11. LINK DOWN POWER SAVING FUNCTION.......................................................................................................................7
6. SWITCH CORE FUNCTION DESCRIPTION ................................................................................................................7
6.1. HARDWARE RESET AND SOFTWARE RESET FUNCTION .................................................................................................7
6.1.1. Hardware Reset .................................................................................................................................................7
6.1.2. Software Reset....................................................................................................................................................7
6.2. LAYER 2 LEARNING AND FORWARDING FUNCTION ......................................................................................................7
6.2.1. Forwarding........................................................................................................................................................8
6.2.2. Learning.............................................................................................................................................................8
6.2.3. Address Table Aging ..........................................................................................................................................8
6.2.4. Layer 2 Multicast...............................................................................................................................................8
6.3. MAC LIMIT FUNCTION ................................................................................................................................................8
6.4. RESERVED MULTICAST ADDRESS HANDLING FUNCTION .............................................................................................9
6.5. IEEE 802.3X FLOW CONTROL FUNCTION ....................................................................................................................9
6.6. HALF DUPLEX BACKPRESSURE FUNCTION.................................................................................................................10
6.6.1. Collision-Based Backpressure (Jam Mode).....................................................................................................10
6.6.2. Carrier-Based Backpressure (Defer Mode).....................................................................................................11
6.7. VLAN FUNCTION ......................................................................................................................................................11
6.7.1. Port-Based VLAN ............................................................................................................................................12
6.7.2. IEEE 802.1Q Tagged-VID Based VLAN..........................................................................................................12
6.7.3. Insert/Remove/Replace Tag..............................................................................................................................12
6.7.4. Ingress and Egress Rules .................................................................................................................................13
6.8. IEEE 802.1P REMARKING FUNCTION.........................................................................................................................13
6.9. BANDWIDTH CONTROL FUNCTION .............................................................................................................................14
6.9.1. Input Bandwidth Control .................................................................................................................................14
6.9.2. Output Bandwidth Control...............................................................................................................................14
6.10. QUALITY OF SERVICE (QOS) FUNCTION.....................................................................................................................14
6.10.1. Priority Arbitration..........................................................................................................................................14
6.10.2. Port-Based Priority Assignment......................................................................................................................15
6.10.3. IEEE 802.1Q-Based Priority Assignment........................................................................................................15
8-Port 10/100Mbps Ethernet Switch Controller iii Track ID: Rev. 1.0
RTL8309N
Datasheet
6.10.4. DSCP-Based Priority Assignment ...................................................................................................................15
6.10.5. IP Address-Based Priority ...............................................................................................................................15
6.10.6. Internal Priority to Queue ID Table.................................................................................................................15
6.10.7. Weighted Round-Robin ....................................................................................................................................15
6.11. LAYER2 TRAFFIC SUPPRESSION FUNCTION (STORM CONTROL) .................................................................................16
6.12. INPUT & OUTPUT DROP FUNCTION ............................................................................................................................16
6.13. LOOP DETECTION FUNCTION .....................................................................................................................................16
6.14. REALTEK CABLE TESTER FUNCTION ..........................................................................................................................16
6.15. EEPROM CONFIGURATION FUNCTION ......................................................................................................................16
7. INTERFACE DESCRIPTIONS........................................................................................................................................17
7.1. I
2
C MASTER FOR EEPROM AUTO-DOWNLOAD ........................................................................................................17
7.2. SMI INTERFACE FOR EXTERNAL CPU ACCESS...........................................................................................................17
8. LDO REGULATOR...........................................................................................................................................................18
9. ELECTRICAL CHARACTERISTICS............................................................................................................................18
9.1. ABSOLUTE MAXIMUM RATING S .................................................................................................................................18
9.2. RECOMMENDED OPERATING RANGE ..........................................................................................................................18
10. MECHANICAL DIMENSIONS...................................................................................................................19
10.1. PLASTIC QUAD FLAT NO-LEAD PACKAGE 64 LEADS 9X9MM
2
OUTLINE ....................................................................19
11. ORDERING INFORMATION.....................................................................................................................20
8-Port 10/100Mbps Ethernet Switch Controller iv Track ID: Rev. 1.0
RTL8309N
Datasheet
List of Tables
TABLE 1 PIN ASSIGNMENTS TABLE.................................................................................................................................................5
TABLE 2. MEDIA CONNECTION PINS ...............................................................................................................................................1
TABLE 3. PARALLEL LED PINS .......................................................................................................................................................1
TABLE 4. MISCELLANEOUS INTERFACE PINS...................................................................................................................................2
TABLE 5. CONFIGURATION STRAPPING PINS ...................................................................................................................................2
TABLE 6. REGULATOR PINS ............................................................................................................................................................3
TABLE 7. POWER AND GND PINS....................................................................................................................................................4
TABLE 8. RESERVED MULTICAST ADDRESS DEFAULT ACTIONS .....................................................................................................9
TABLE 9. VLAN TABLE................................................................................................................................................................11
TABLE 10. VLAN ENTRY .............................................................................................................................................................12
TABLE 11. SMI (MDC, MDIO) MANAGEMENT PACKET FORMAT ................................................................................................17
TABLE 12. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................18
TABLE 13. RECOMMENDED OPERATING RANGE ...........................................................................................................................18
TABLE 14. ORDERING INFORMATION ............................................................................................................................................20
List of Figures
FIGURE 1. BLOCK DIAGRAM ...........................................................................................................................................................3
FIGURE 2. PIN ASSIGNMENTS ..........................................................................................................................................................4
FIGURE 3. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION ......................................................................................................6
FIGURE 4. TX PAUSE FRAME FORMAT...........................................................................................................................................10
FIGURE 5. FLOW CONTROL STATE MACHINE ................................................................................................................................10
FIGURE 6. COLLISION-BASED BACKPRESSURE SIGNAL TIMING ....................................................................................................11
FIGURE 7. 1KB~16KB EEPROM READ/WRITE TIMING................................................................................................................17
8-Port 10/100Mbps Ethernet Switch Controller v Track ID: Rev. 1.0
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