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1 of 19 September 18, 2007
Document Number EDCS-540123
Revision Revision 1.2
QSGMII Specification
The Quad Serial Gigabit Media Independent Interface (QSGMII) is designed to satisfy the
following requirements:
• Convey 4 ports of network data and port speed between a 10/100/1000 PHY and a MAC
with significantly less signal pins than required for GMII & SGMII.
• Operate in both half and full duplex and at all port speeds.
• This implementation can be extended to other port to channel ratios. However, this is
outside the scope of this document.

QSGMII Specification: EDCS-540123 Revision 1.2
2 of 19 September 18, 2007
Change History
Definitions
MII – Media Independent Interface: A digital interface that provides a 4-bit wide datapath
between a 10/100 Mbit/s PHY and a MAC sublayer. Since MII is a subset of GMII, in this
document, we will use the term “GMII” to cover all of the specification regarding the MII
interface.
GMII – Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide
datapath between a 1000 Mbit/s PHY and a MAC sublayer. It also supports the 4-bit wide MII
interface as defined in the IEEE 802.3z specification. In this document, the term “GMII”
covers all 10/100/1000 Mbit/s interface operations.
SGMII – Serial Gigabit Media Independent Interface: A digital interface that provides a 1.25
Gbps serial dual-data-rate datapath between a 1000 Mbit/s PHY and a MAC sublayer. Refer to
ENG-46158 or ftp://ftp-eng.cisco.com/smii/smii.html for details.
Revision Date Description Author
1.2 Spetember 7,2007 Updated Bit[13] and Bit[0] on Table3
and added a statement of possible
removal of the first byte of frame in 10/
100Mbit/s operation to match SGMII
spec.
Akin Koyuncuoglu
1.1 June 20, 2007 Reword Note1, Added a requirement to
disable running disparity check at
receiver.
Akin Koyuncuoglu
1.0 April 17, 2007 Updated Interconnect Loss Template-
Figure 11 and Channel Loss Budget-
Table 9. Updated Differential and com
-
mon mode return loss parameters and
differential voltage values in electrical
section.
Akin Koyuncuoglu,
Warren Meggitt
0.5 January 4, 2007 Updated PCS Receive for carrier_detect
function. Updated /I/ Idle Code Group
Selection for Transmission. Added a note
for running disparity support by Framers.
Updated Figure2, Figure4,
Figure5,Figure6, Table1 and Table2
Akin Koyuncuoglu
0.4 December 4, 2006 Updated legal section in the end of the
document
Akin Koyuncuoglu
0.3 September 1, 2006 Updated Electrical Specification Akin Koyuncuoglu,
Warren Meggitt
0.2 Nov. 3, 2005 Initial Release Jeff Provost

3 of 19 September 18, 2007
Overview
QSGMII uses two data signals in each direction to convey frame data and link rate information
between a multi-port 10/100/1000 PHY and Ethernet MAC. The data signals operate at 5.0
Gbps using CDR technology to recover the clock at the MAC and PHY interfaces. Due to the
high speed of operation, each of these signal pairs are realized as differential pairs thus
optimizing signal integrity while minimizing system noise.
Figure 1 compares the IEEE 802.3 PCS reference diagram before and after the QSGMII
modification.
Figure 1 “Standard” and Modified Transmit Path Diagrams per IEEE 802.3 PCS/PMA
TXD<7:0>
GMII
tx_Config_Reg<D7:D0>
tx_Config_Reg<D15:D8>
7 6 5 4 3 2 1 0
(125 million octets/s)
8 + control
H G F E D C B A
Input to ENCODE function
8B/10B
Encoder
a b c d e i f g h j
10
0 1 2 3 4 5 6 7 8 9
Management Registers
PMA Service Interface
tx_code-group<9:0>
PCS ENCODE function
PMD Service Interface
(1250 million tx_bits/s)
bit 0 is transmitted first
IEEE 802.3 Figure 36-3-PCS reference diagram
TXD<7:0>
GMII
tx_Config_Reg<D7:D0>
tx_Config_Reg<D15:D8>
7 6 5 4 3 2 1 0
(125 million octets/s)
8 + control
H G F E D C B A
Input to ENCODE function
8B/10B
Encoder
a b c d e i f g h j
10
0 1 2 3 4 5 6 7 8 9
Management Registers
PMA Service Interface
(500 million code-groups/s)
tx_code-group<9:0>
PCS ENCODE function
Output of ENCODE function
PMD Service Interface
(5000 million tx_bits/s)
bit 0 is transmitted first
QSGMII Modified Figure 36-3-PCS reference diagram
Port 0
1
2
3
no swapper
“K28.5”
Swapper
Swapper operates on
8 + control
ports 1, 2, 3
2-bit free-running counter
(changes are shown with italicized text)
octets + control
8 + control
Output of ENCODE function
(125 million code-groups/s)

QSGMII Specification: EDCS-540123 Revision 1.2
4 of 19 September 18, 2007
The IEEE 802.3 reference diagrams in Figure 2 shows where the modification to the receive
PCS function occurs.
The transmit and receive data paths leverage the 1000BASE-X PCS defined in the IEEE
802.3z specification (clause 36). Four ports of traditional GMII data signals (TXD/RXD), data
valid signals (TX_EN/RX_DV), and error signals (TX_ER/RX_ER) are muxed, encoded, and
serialized. Carrier Sense (CRS) is derived/inferred from RX_DV, and collision (COL) is
logically derived in the MAC when RX_DV and TX_EN are simultaneously asserted. There is
a small block in the PHY transmit path to suppress TX_ER in full duplex mode when TX_EN
is not asserted. Since four 1.25Gbps SGMII ports are interleaved onto a single link, the data-
rate becomes 5.0 Gbps.
Figure 2 “Standard” and Modified Receive Path Diagram per IEEE 802.3 PCS/PMA
RXD<7:0>
GMII
7 6 5 4 3 2 1 0
(125 million octets/s)
8 + control
H G F E D C B A
Output of DECODE function
8B/10B
Decoder
a b c d e i f g h j
10
0 1 2 3 4 5 6 7 8 9
PMA Service Interface
(125 million code-groups/s)
rx_code-group<9:0>
PCS DECODE function
Input to DECODE function
PMD Service Interface
(1250 million rx_bits/s)
bit 0 is received first
IEEE 802.3 Figure 36-3-PCS reference diagram
0 0 1 1 1 1 1 x x x
Properly aligned comma+symbol
RXD<7:0>
GMII
rx_Config_Reg<D7:D0>
rx_Config_Reg<D15:D8>
7 6 5 4 3 2 1 0
(500 million octets/s)
8 + control + carrier_detect
H G F E D C B A
Output of DECODE function
a b c d e i f g h j
10
0 1 2 3 4 5 6 7 8 9
Management Registers
PMA Service Interface
(500 million code-groups/s)
rx_code-group<9:0>
PCS DECODE & carrier_detect
Input to DECODE function
PMD Service Interface
(5000 million rx_bits/s)
bit 0 is received first
0 0 1 1 1 1 1 x x x
Properly aligned comma+symbol
Swapper
ports 1, 2, 3
“K28.1”
K28.1 detect
0
1
2
3
QSGMII Modified Figure 36-3-PCS reference diagram
(changes are shown with italicized text)
rx_Config_Reg<D7:D0>
rx_Config_Reg<D15:D8>
Management Registers
8B/10B
Decoder &
carrier_detect
function
clear
8 + control+carrier detect
2-bit counter
function
*See Note1
disparityEN
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