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MHL

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Pin Mapping ......................................................................................................................................................................... 2

Functional Description ......................................................................................................................................................... 3

MHL/HDMI Receiver Block ............................................................................................................................................ 3

CBUS Control Block ........................................................................................................................................................ 3

HDCP Register Block ....................................................................................................................................................... 4

OTP ROM Block .............................................................................................................................................................. 4

HDCP Authentication Logic Block .................................................................................................................................. 4

Data Path and HDCP Unmask Blocks .............................................................................................................................. 4

DDC Interface................................................................................................................................................................... 4

CEC Interface ................................................................................................................................................................... 4

10 to 8 Bit Dither .......................................................................................................................................................... 6

Mux 656 ........................................................................................................................................................................ 6

Video Timing ................................................................................................................................................................ 6

Digital Parallel Video Output Interface ............................................................................................................................ 6

Automatic Video Configuration Logic Block ................................................................................................................... 7

Audio Output Logic Block ............................................................................................................................................... 7

Automatic Audio Configuration Logic Block .................................................................................................................. 7

Registers, Configuration, and Interrupt Logic Block ........................................................................................................ 7

Local I

C Slave Logic Block ............................................................................................................................................ 7

Target AC Specification ................................................................................................................................................. 13

Video Output Timings ................................................................................................................................................ 14

Audio Output Timings ................................................................................................................................................ 14

Miscellaneous Timings ............................................................................................................................................... 16

Interrupt Timings ........................................................................................................................................................ 17

Timing Diagrams ................................................................................................................................................................ 19

Digital Video Output Timing Diagrams ......................................................................................................................... 19

Output Transition Times ............................................................................................................................................. 19

Output Clock to Output Data Delay ........................................................................................................................... 20

Digital Audio Output Timings ........................................................................................................................................ 20

Digital Audio Output Pins .............................................................................................................................................. 26

Control and Configuration Pins ...................................................................................................................................... 26

Power and Ground Pins .................................................................................................................................................. 27

Feature Information ............................................................................................................................................................ 28

MHL 24-bit Mode ........................................................................................................................................................... 28

MHL Packed Pixel Mode ............................................................................................................................................... 28

Audio Output Interface ................................................................................................................................................... 29

Video Output Mode Configuration ................................................................................................................................. 32

System Design Guidelines .................................................................................................................................................. 43

HDMI/MHL Design Application .................................................................................................................................... 43

Power Supply Decoupling .............................................................................................................................................. 44

High-speed TMDS Signals ............................................................................................................................................. 45

Packaging ............................................................................................................................................................................ 46

ePad Requirements ......................................................................................................................................................... 46

Package Dimensions ....................................................................................................................................................... 47

Marking Specification..................................................................................................................................................... 48

Figure 5. Test Point VDDTP for VDD Noise Tolerance Specification .............................................................................. 10

Figure 6. Audio Crystal Schematic ..................................................................................................................................... 15

Figure 7. SCDT and CKDT Timing from DE or RXC Inactive/Active ............................................................................. 18

Figure 8. RESET_N Minimum Timings............................................................................................................................. 19

Figure 9. RESET_N to VDD Timing ................................................................................................................................. 19

Figure 10. Digital Output Transition Times ....................................................................................................................... 19

Figure 11. Video Digital Output Transition Times ............................................................................................................. 19

Figure 12. Receiver Clock-to-Output Delay and Duty Cycle Limits .................................................................................. 20

Figure 13. I

Figure 14. TDM Output Timings ........................................................................................................................................ 21

Figure 21. TDM – Delay of First Channel MSB to FS ....................................................................................................... 30

Figure 22. 4:4:4 Timing Diagram ....................................................................................................................................... 33

Figure 23. YCbCr Timing Diagram .................................................................................................................................... 35

Figure 24. YCbCr 4:2:2 Embedded Sync Timing Diagram ................................................................................................ 37

Figure 25. YCbCr Mux 4:2:2 Timing Diagram .................................................................................................................. 39

Figure 26. YCbCr Mux 4:2:2 Embedded Sync Encoding Timing Diagram ....................................................................... 41

Figure 27. 12-bit Output 4:4:4 Timing Diagram ................................................................................................................ 42

Figure 28. Connection of MHL and HDMI Port ................................................................................................................ 43

Figure 29. Decoupling and Bypass Schematic ................................................................................................................... 44