B27A_Fortis_Flash_512Gb_1Tb_2Tb_4Tb_Async_Sync_NAND_Datasheet.pdf_micronTLCdatasheet

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NAND Flash Memory - FortisFlash™

MT29F512G08EBHBF, MT29F1T08EEHBF, MT29F2T08EMHBF,

MT29F4T08EUHBF

B27A FortisFlash™ Features

• Open NAND Flash Interface (ONFI) 4.0-compliant

• JEDEC NAND Flash Interoperability (JESD230C)

compliant

• Triple-level cell (TLC)

• Organization

– Page size x8: 18,592 bytes (16,384 + 2208 bytes)

– Block size: 5184 pages, (82,944K + 11,178K bytes)

– Plane size: 4 planes x 236 blocks

– Device size: 512Gb: 944 blocks; 1Tb: 1888 blocks;

2Tb: 3776 blocks; 4Tb: 7552 blocks

• NV-DDR3 I/O performance

– Up to NV-DDR3 timing mode 10

– Clock rate: 2.5ns (NV-DDR3)

– Read/write throughput per pin: 800 MT/s

• NV-DDR2 I/O performance

– Up to NV-DDR2 timing mode 8

– Clock rate: 3.75ns (NV-DDR2)

– Read/write throughput per pin: 533 MT/s

• Asynchronous I/O performance

– Up to asynchronous timing mode 5

–

RC/

WC: 20ns (MIN)

– Read/write throughput per pin: 50 MT/s

• TLC Array performance

– SNAP READ operation time: 52µs (TYP)

– READ PAGE operation time: 88µs (TYP)

– Effective Program page time: 800µs (TYP)

– Erase block time: 15ms (TYP)

• Operating Voltage Range

– V

: 2.7–3.6V

– V

CCQ

: 1.14–1.26V, 1.7–1.95V

• Command set: ONFI NAND Flash Protocol

• Data is required to be randomized by the external

host prior to being inputted to the NAND device

• First block (block address 00h) is valid when ship-

ped from factory. For minimum required ECC, see

Error Management (page 224).

• RESET (FFh) required as first command after pow-

er-on

• Operation status byte provides software method for

detecting

– Operation completion

– Pass/fail condition

– Write-protect status

• Data strobe (DQS) signals provide a hardware meth-

od for synchronizing data DQ in the NV-DDR2/NV-

DDR3 interface

• Copyback operations supported within the plane

from which data is read

• On-die Termination (ODT)

• Quality and reliability

– Testing methodology: JESD47

– Data retention: See qualification report – May

vary for targeted application

– TLC Endurance: 2000 PROGRAM/ERASE cycles

– SLC Endurance: 40,000 PROGRAM/ERASE cycles

• Operating temperature:

– Commercial: 0°C to +70°C

• Package

– 132-ball BGA

Notes:

1. The ONFI 4.0 specification is available at

www.onfi.org.

2. The JEDEC specification is available at

www.jedec.org/standards-documents.

3. NV-DDR3 functionality is only available with

1.2V V

CCQ

4. NV-DDR2 and Asynchronous functionality is

only available with 1.8V V

CCQ

5. ODT functionality is supported only in NV-

DDR2 and NV-DDR3 mode.

6. Read Retry and Auto Read Calibration oper-

ations are required to achieve specified en-

durance and for general array data integri-

ty.

7. For minimum required ECC, see Error Man-

agement (page 224).

Micron Confidential and Proprietary Advance

‡

TLC 512Gb-4Tb NAND

B27A FortisFlash™ Features

PDF

B27A_Fortis_512Gb_1Tb_2Tb_4Tb_NAND_Datasheet.pdf - Rev. K 4/17/2019 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.

Release: 4/17/19

Contents

Important Notes and Warnings ....................................................................................................................... 14

General Description ....................................................................................................................................... 15

Asynchronous, NV-DDR2, NV-DDR3 Signal Descriptions ................................................................................. 15

Signal Assignments ......................................................................................................................................... 17

Package Dimensions ....................................................................................................................................... 18

Architecture ................................................................................................................................................... 20

Device and Array Organization ........................................................................................................................ 21

Bus Operation – Asynchronous Interface ......................................................................................................... 28

Asynchronous Enable/Standby ................................................................................................................... 28

Asynchronous Bus Idle ............................................................................................................................... 28

Asynchronous Pausing Data Input/Output .................................................................................................. 29

Asynchronous Commands .......................................................................................................................... 29

Asynchronous Addresses ............................................................................................................................ 30

Asynchronous Data Input ........................................................................................................................... 31

Asynchronous Data Output ......................................................................................................................... 32

Write Protect .............................................................................................................................................. 33

Ready/Busy# .............................................................................................................................................. 33

Bus Operation – NV-DDR2 Interface ................................................................................................................ 36

Differential Signaling .................................................................................................................................. 37

Warmup Cycles .......................................................................................................................................... 37

On-die Termination (ODT) ......................................................................................................................... 38

Self-termination On-die Termination (ODT) ................................................................................................ 40

Matrix Termination .................................................................................................................................... 41

Matrix Termination Examples ..................................................................................................................... 44

NV-DDR2 Standby ...................................................................................................................................... 48

NV-DDR2 Idle ............................................................................................................................................ 49

NV-DDR2 Pausing Data Input/Output ......................................................................................................... 49

NV-DDR2 Commands ................................................................................................................................. 49

NV-DDR2 Addresses ................................................................................................................................... 50

NV-DDR2 Data Input .................................................................................................................................. 51

NV-DDR2 Data Output ............................................................................................................................... 52

Write Protect .............................................................................................................................................. 53

Ready/Busy# .............................................................................................................................................. 53

Bus Operation – NV-DDR3 Interface ................................................................................................................ 54

On-Die Termination ................................................................................................................................... 54

Device Initialization ....................................................................................................................................... 57

Initialization ......................................................................................................................................... 59

Electronic Mirroring ....................................................................................................................................... 60

Activating Interfaces ....................................................................................................................................... 63

Activating the Asynchronous Interface ........................................................................................................ 63

Activating the NV-DDR2 Interface ............................................................................................................... 63

Activating the NV-DDR3 Interface ............................................................................................................... 64

CE# Pin Reduction and Volume Addressing ..................................................................................................... 65

Initialization Sequence ............................................................................................................................... 67

Volume Appointment Without CE# Pin Reduction ....................................................................................... 70

Appointing Volume Addresses ..................................................................................................................... 70

Selecting a Volume ..................................................................................................................................... 71

Multiple Volume Operation Restrictions ...................................................................................................... 71

Volume Reversion ....................................................................................................................................... 72

Command Definitions .................................................................................................................................... 74

Micron Confidential and Proprietary Advance

TLC 512Gb-4Tb NAND

B27A FortisFlash™ Features

PDF

B27A_Fortis_512Gb_1Tb_2Tb_4Tb_NAND_Datasheet.pdf - Rev. K 4/17/2019 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Release: 4/17/19

Reset Operations ............................................................................................................................................ 77

RESET (FFh) ............................................................................................................................................... 77

SYNCHRONOUS RESET (FCh) .................................................................................................................... 78

RESET LUN (FAh) ....................................................................................................................................... 79

HARD RESET (FDh) .................................................................................................................................... 80

Identification Operations ................................................................................................................................ 82

READ ID (90h) ............................................................................................................................................ 82

READ ID Parameter Tables .......................................................................................................................... 84

READ PARAMETER PAGE (ECh) .................................................................................................................. 85

Parameter Page Data Structure Tables ..................................................................................................... 87

READ UNIQUE ID (EDh) ........................................................................................................................... 100

Configuration Operations .............................................................................................................................. 102

SET FEATURES (EFh) ................................................................................................................................. 103

GET/SET FEATURES by LUN (D4h/D5h) .................................................................................................... 104

Feature Address Details ............................................................................................................................. 105

SLC Operations ......................................................................................................................................... 121

Configuration using SET FEATURES ....................................................................................................... 121

Configuration using Commands (DAh, DFh) .......................................................................................... 121

SLC/TLC Mode Operations .................................................................................................................... 122

VOLUME SELECT (E1h) ............................................................................................................................. 123

ODT CONFIGURE (E2h) ............................................................................................................................ 124

ZQ Calibration ........................................................................................................................................... 128

ZQ Calibration Long (F9h) ..................................................................................................................... 129

ZQ Calibration Short (D9h) .................................................................................................................... 130

ZQ external resistor value, tolerance, and capacitive loading ................................................................... 131

Status Operations .......................................................................................................................................... 133

READ STATUS (70h) .................................................................................................................................. 135

READ STATUS ENHANCED (78h) ............................................................................................................... 135

FIXED ADDRESS READ STATUS ENHANCED (71h) .................................................................................... 136

Column Address Operations .......................................................................................................................... 137

CHANGE READ COLUMN (05h-E0h) ......................................................................................................... 137

CHANGE READ COLUMN ENHANCED (06h-E0h) ...................................................................................... 138

CHANGE READ COLUMN ENHANCED (00h-05h-E0h) Operation ............................................................... 139

CHANGE WRITE COLUMN (85h) ............................................................................................................... 139

CHANGE ROW ADDRESS (85h) .................................................................................................................. 140

Read Operations ............................................................................................................................................ 142

READ MODE (00h) .................................................................................................................................... 145

READ PAGE (00h-30h) ............................................................................................................................... 146

READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 147

READ PAGE CACHE RANDOM (00h-31h) ................................................................................................... 148

READ PAGE CACHE LAST (3Fh) ................................................................................................................. 150

READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 151

Read Retry Operations ............................................................................................................................... 152

Read Retry Scratch Space ....................................................................................................................... 154

SNAP READ ............................................................................................................................................... 155

Snap Read Feature ................................................................................................................................. 155

SNAP READ MULTI-PLANE (00h-32h) - CROSS PLANE SNAP READ ........................................................ 157

READ OFFSET Operations ......................................................................................................................... 159

Auto Read Calibration Operations .............................................................................................................. 161

Auto Read Calibration ............................................................................................................................ 162

Auto Read Calibration and Read Offset ................................................................................................... 164

Reading Out Calibrated Offsets With GET FEATURES (EEh/D4h) ............................................................. 165

Micron Confidential and Proprietary Advance

TLC 512Gb-4Tb NAND

B27A FortisFlash™ Features

PDF

B27A_Fortis_512Gb_1Tb_2Tb_4Tb_NAND_Datasheet.pdf - Rev. K 4/17/2019 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Release: 4/17/19

Soft Data Read Operations ......................................................................................................................... 166

READ PAGE with SOFT INFORMATION (33h-30h) .................................................................................. 167

SOFT INFORMATION READOUT (36h) .................................................................................................. 168

SOFT INFORMATION READOUT (36h) with the Level Indicator Bit ......................................................... 170

Single Bit Soft Bit Read Operations ............................................................................................................. 175

SINGLE BIT SOFT BIT READ PAGE (00h-34h) ......................................................................................... 177

SINGLE BIT SOFT BIT READ PAGE CACHE RANDOM (00h-38h) ............................................................. 179

Word Line Status Bypass ............................................................................................................................ 182

TLC Two Pass Programming (2-8) ................................................................................................................... 184

PROGRAM PAGE (80h-10h) ........................................................................................................................ 186

PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 188

PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................ 190

PROGRAM SUSPEND (84h) and PROGRAM RESUME (13h) ......................................................................... 194

Multiple Page Data Entry during Cache Programming ................................................................................. 196

Erase Operations ........................................................................................................................................... 198

ERASE BLOCK (60h-D0h) ........................................................................................................................... 198

ERASE BLOCK MULTI-PLANE (60h-D1h) ................................................................................................... 199

ERASE BLOCK MULTI-PLANE (60h-60h-D0h) ............................................................................................ 199

ERASE SUSPEND (61h) and ERASE RESUME (D2h) .................................................................................... 200

Nested Suspend ............................................................................................................................................ 203

Copyback Operations .................................................................................................................................... 206

COPYBACK READ (00h-35h) ...................................................................................................................... 207

COPYBACK PROGRAM (85h–10h) .............................................................................................................. 209

COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 212

COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 213

One-Time Programmable (OTP) Operations ................................................................................................... 216

PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 217

PROTECT OTP AREA (80h-10h) .................................................................................................................. 219

READ OTP PAGE (00h-30h) ........................................................................................................................ 220

Multi-Plane Operations ................................................................................................................................. 221

Multi-Plane Addressing ............................................................................................................................. 221

Interleaved Die (Multi-LUN) Operations ......................................................................................................... 222

Error Management ........................................................................................................................................ 224

External Data Randomization .................................................................................................................... 225

Shared Pages - TLC ........................................................................................................................................ 226

Output Drive Impedance ............................................................................................................................... 235

AC Overshoot/Undershoot Specifications ....................................................................................................... 240

Input Slew Rate ............................................................................................................................................. 242

Output Slew Rate ........................................................................................................................................... 250

Power Cycle and Ramp Requirements ............................................................................................................ 252

Electrical Specifications ................................................................................................................................. 253

Package Electrical Specification and Pad Capacitance ................................................................................. 253

Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 256

Electrical Specifications – DC Characteristics and Operating Conditions (NV-DDR2, NV-DDR3) ....................... 258

Electrical Specifications – DC Characteristics and Operating Conditions (V

CCQ

) ............................................... 263

Single-Ended Requirements for Differential signals ..................................................................................... 267

Testing Conditions ........................................................................................................................................ 268

Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 270

Electrical Specifications – AC Characteristics and Operating Conditions (NV-DDR2, NV-DDR3) ........................ 272

Electrical Specifications – Array Characteristics .............................................................................................. 289

Asynchronous Interface Timing Diagrams ...................................................................................................... 293

NV-DDR2 and NV-DDR3 Interface Timing Diagrams ...................................................................................... 301

Micron Confidential and Proprietary Advance

TLC 512Gb-4Tb NAND

B27A FortisFlash™ Features

PDF

B27A_Fortis_512Gb_1Tb_2Tb_4Tb_NAND_Datasheet.pdf - Rev. K 4/17/2019 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Release: 4/17/19