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JESD209B ddr4协议
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JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD209B
FEBRUARY 2010
JEDEC
STANDARD
Low Power Double Data Rate (LPDDR)
SDRAM Standard
(Revision of JESD209A, February 2009)
SPECIAL DISCLAIMER: JEDEC has received
information that certain patents or patent applications
may be essential to this standard. However, as of the
publication date of this standard, no statements
regarding an assurance or refusal to license such
patents or patent applications have been provided.
Contact JEDEC for further information.
JEDEC does not make any determination as to the
validity or relevancy of such patents or patent
applications. Anyone making use of the standard
assumes all liability resulting from such use. JEDEC
disclaims any representation or warranty, express or
implied, relating to the standard and its use.
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NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and approved
through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the
proper product for use by those other than JEDEC members, whether the standard is to be used either
domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption may
involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to
any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or
publications.
The information included in JEDEC standards and publications represents a sound approach to product
specification and application, principally from the solid state device manufacturer viewpoint.
No claims to be in conformance with this standard may be made unless all requirements stated in the
standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should
be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA
22201-3834, (703)907-7559 or www.jedec.org.
Published by
©JEDEC Solid State Technology Association 2007
2500 Wilson Boulevard
Arlington, VA 22201-3834
This document may be downloaded free of charge, however JEDEC retains the copyright on this material.
By downloading this file the individual agrees not to charge for or resell the resulting material.
Price: Please refer to the current
Catalog of JEDEC Engineering Standards and Publications or www.jedec.org.
Documents, USA and Canada (1-800-854-7179), International (303-397-7956)
Printed in the U.S.A.
All rights reserved
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PLEASE!
DON'T VIOLATE
THE
LAW!
This document is copyrighted by the JEDEC Solid State Technology Association
and may not be
reproduced without permission.
Organizations may obtain permission to reproduce a limited number of copies
through entering into a license agreement. For information, contact:
JEDEC Solid State Technology Association
3103 North 10th Street, Suite 240 South
Arlington, Virginia 22201-2107
or call (703) 907-7559
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Special Disclaimer
JEDEC has received information that certain patents or patent applications
may be essential to this standard. However, as of the publication date of this
standard, no statements regarding an assurance or refusal to license such
patents or patent applications have been provided. Contact JEDEC for further
information.
JEDEC does not make any determination as to the validity or relevancy of such
patents or patent applications. Anyone making use of the standard assumes all
liability resulting from such use. JEDEC disclaims any representation or
warranty, express or implied, relating to the standard and its use.
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JEDEC Standard No. 209B
Contents
1 Scope ........................................................................................................................................1
2 Low-Power Double Data Rate (LPDDR) SDRAM Devices ...................................................2
2.1 Features..................................................................................................................................2
2.2 General Description ...............................................................................................................2
2.2.1 Packages..............................................................................................................................4
2.3 Terminology and Definitions.................................................................................................9
3 Functional Description............................................................................................................10
3.1 Initialization ........................................................................................................................10
3.1.0.1 TQ Signal Initialization .................................................................................................13
3.2 Register Definition...............................................................................................................13
3.2.1 Mode Register ..................................................................................................................13
3.2.1.1 Burst Length ..................................................................................................................14
3.2.1.2 Burst Type .....................................................................................................................16
3.2.1.3 Read Latency .................................................................................................................16
3.2.2 Extended Mode Register ..................................................................................................16
3.2.2.1 Partial Array Self Refresh (Optional) ...........................................................................17
3.2.2.2 Temperature Compensated Self Refresh (Optional) .....................................................17
3.2.2.3 Output Drive Strength ...................................................................................................17
3.2.3 Status Register Read (Optional)........................................................................................18
3.2.4 Temperature Output Signal (optional)..............................................................................20
4 Commands ..............................................................................................................................21
5 Operation.................................................................................................................................26
5.1 Deselect ...............................................................................................................................26
5.2 No Operation .......................................................................................................................26
5.3 Mode Register Set ...............................................................................................................26
5.4 Active ..................................................................................................................................27
5.5 Read ....................................................................................................................................28
5.5.1 Read to Read ....................................................................................................................30
5.5.2 Read Burst Terminate ......................................................................................................30
5.5.3 Read to Write ...................................................................................................................30
5.5.4 Read to Precharge ............................................................................................................30
5.5.5 Burst Terminate ................................................................................................................34
5.6 Write ....................................................................................................................................34
5.6.1 Write to Write ..................................................................................................................37
5.6.2 Write to Read ...................................................................................................................37
5.6.3 Write to Precharge: ..........................................................................................................37
5.7 Precharge .............................................................................................................................41
5.8 Auto Precharge ....................................................................................................................42
5.9 Refresh Requirements .........................................................................................................42
5.10 Auto Refresh .....................................................................................................................42
5.11 Self Refresh ........................................................................................................................42
-i-
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