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Document Number
DS40210
Rev 2-2
PI7C9X2G608GP
PCI EXPRESS GEN 2 PACKET SWITCH
6-Port/ 8-Lane PCI Express Gen 2 Switch
Green Package Family
DATASHEET
REVISION 2-2
September 2017
1545 Barber Lane, Milpitas, CA 95035
Telephone: 408-435-0800
FAX: 408-435-1100
Internet: http://www.diodes.com
PI7C9X2G608GP Page 2 of 117
October 2017
Document Number
DS40210
Rev 2-2
www.diodes.com
© Diodes Incorporated
PI7C9X2G608GP
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS
DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or
other changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any
liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated
convey any license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products
described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the
companies whose products are represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized
sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall
indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized
application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names
and markings noted herein may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this
document is the final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems
without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use
provided in the labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected
to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or
systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements
concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems,
notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further,
Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes
Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
PI7C9X2G608GP Page 3 of 117
October 2017
Document Number
DS40210
Rev 2-2
www.diodes.com
© Diodes Incorporated
PI7C9X2G608GP
REVISION HISTORY
Date Revision Number Description
04/08/13 0.1 Preliminary Datasheet
01/06/14 0.2 Updated Section 1 Features
Updated Section 2 General Description
Updated Section 3 Pin Description Updated
Updated Section 3.2 Port Specific Signals
Updated Section 4.1 Pin List of 196-Pin LBGA
Updated Section 5.3 Port-Lane Mapping
Added Section 7 Register Description
Updated Section 9 Clock Scheme
Updated Section 11.3 Power Consumption
Updated Section 12 Package Information
Updated Section 13 Ordering Information
06/09/14 1.0 Updated Section 1 Features
Updated Section 3 Pin Description
Updated Section 3.1 PCI Express Interface Signals
Updated Section 3.2 Port Specific Signals
Updated Section 3.4 Miscellaneous Signals
Updated Section 4.1 Pin List of 196-Pin LBGA
Updated Section 7 EEPROM Interface (change 7.1 to 7)
Updated Section 7.2 SMBus Interface remove
Updated Section 7.3 EEPROM Space address map
Updated and Added Section 8.2 Transparent Mode Configuration Registers (Remove SMBUS)
Updated Section 9 Clock Scheme
Updated Section 11.3 Power Consumption
10/16/14 1.1 Added Section 7.2 SMBUS Interface
Added Section 7.3 I2C Slave Interface
Added Section 9 Clock Scheme
Updated Section 1 Features
Updated Section 2 General Description
Updated Section 3.2 Port Specific Signals
Updated Section 3.3 EEPROM and SMBUS/I2C Signals
Updated Section 3.4 Miscellaneous Signals
Updated Section 4 Pin Assignment
Updated Section 7.1 EEPROM Interface
Updated Section 7.2 SMBus Interface
Updated Section 7.3 I
2
C Slave Interface
Deleted Section 7.4 EEPROM Mode At Reset
Deleted Section 7.5 EEPROM Space Address Map
Updated Section 8.2 Transparent Mode Configuration Registers
Updated Section 9 Clock Scheme
Updated Section 10 Power Management
12/10/14 1.2 Updated Section 1 Features
Updated Section 3.2 Port Specific Signals
Updated Section 3.4 Miscellaneous Signals
Updated Section 4.1 PIN LIST of 196-PIN LBGA
Updated Figure 4 1 PI7C9X2G608GP Ball Assignment (Transparent Top View)
Updated Table 9.2 AC Switching Characteristics
12/23/14 1.3 Updated Section 4-1 PIN LIST of 196-PIN LBGA
08/24/15 1.4 Updated Section 3 Pin Description
Updated Section 4 Pin Assignment
Updated Section 6.1 Physical Layer Circuit
Updated Section 7.1 EEPROM Interface
Updated Section 7.2 SMBus Interface
Updated Section 8.2 Transparent Mode Configuration Registers
Updated Section 9 Clock Scheme
Updated Section 11.2 DC Specifications
09/15/15 1.5 Updated Table 11-1 Absolute Maximum Ratings
12/23/15 1.6 Updated Section 3 Pin Description
PI7C9X2G608GP Page 4 of 117
October 2017
Document Number
DS40210
Rev 2-2
www.diodes.com
© Diodes Incorporated
PI7C9X2G608GP
Updated Table 7-5 SMBUS Block Write Portion
Updated Figurate 7-11& 7-13 I2C Read Command Packet
Updated Section 8.2.48 XPIP_CSR0 Register
Updated Section 8.2.59 XPIP_CSR5 Register
Updated Section 8.2.60 TL_CSR Register
Updated Section 8.2.77 PCI Express Capabilities Register
Updated Section 8.2.84 Slot Capabilities Register
Updated Section 8.2.109 Port VC Capability Register 1
Updated Table 11-1 Absolution Maximum Ratings
Updated Table 11-2 DC Electrical Characteristics
02/25/16 1.7 Added Section 11 Power Sequence
08/25/16 1.8 Updated Section 1 Features
Updated Section 3-2 Port Specific Signals (19 balls)
Updated Section 5-3 Port-Lane Mapping
Updated Section 7.1.4 Mapping EEPROM Contents To Configuration Registers
Updated Section 8.2.17 Memory Base Address Register – OFFSET 20h
Updated Section 8.2.52 SWITCH OPERATION MODE – OFFSET 74h (Upstream Port Only)
Updated Section 8.2.53 SWITCH OPERATION MODE – OFFSET 74h (Downstream Port Only)
Updated Section 8.2.59 XPIP_CSR5 – OFFSET 88h
Updated Section 8.2.63 OPERATION MODE – OFFSET 98h
Updated Section 8.2.81 LINK CAPABILITIES REGISTER – OFFSET CCh
Updated Section 8.2.83 Link Status Register – OFFSET D0h
Updated Section 8.2.140 SMBUS Control Register – OFFSET 344h (Upstream Port Only)
Updated Section 8.2.144 POWER DAVING DISABLE RGISTER – OFFSET 360h
Updated Table 12.3 Power Consumption
09/19/17 2-2 Updated Section 3.3 EEPROM and SMBUS/I2C SIGNALS (6 balls)
Updated Section 3.4 MISCELLANEOUS SIGNALS (30 balls)
Updated Section 7.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS
Updated Section 8.2 TRANSPARENT MODE CONFIGURATION REGISTERS
Updated Section 12.1 Absolute Maximum Ratings
Updated Table 12-2 DC electrical characteristics
Updated Table 12.4 Power Consumption
Added Section 12.5 Operating Ambient Temperature
Added Section 13 Thermal Data
Revision numbering system changed to whole number
PI7C9X2G608GP Page 5 of 117
October 2017
Document Number
DS40210
Rev 2-2
www.diodes.com
© Diodes Incorporated
PI7C9X2G608GP
TABLE OF CONTENTS
1
FEATURES ........................................................................................................................................................ 11
2
GENERAL DESCRIPTION ............................................................................................................................... 12
3
PIN DESCRIPTION ........................................................................................................................................... 14
3.1
PCI
EXPRESS
INTERFACE
SIGNALS
(65
BALLS
) .................................................................................. 14
3.2
PORT
SPECIFIC
SIGNALS
(19
BALLS
) .................................................................................................... 15
3.3
EEPROM
AND
SMBUS/I2C
SIGNALS
(6
BALLS
) ..................................................................................... 16
3.4
MISCELLANEOUS
SIGNALS
(30
BALLS
) ............................................................................................... 16
3.5
POWER
PINS
(76
BALLS
) ........................................................................................................................... 17
4
PIN ASSIGNMENT ........................................................................................................................................... 18
4.1
PIN
LIST
OF
196-PIN
LBGA ...................................................................................................................... 18
5
MODE SELECTION AND PORT-LANE MAPPING ...................................................................................... 20
5.1
MODE
SELECTION .................................................................................................................................. 20
5.2
LANE
MAPPING ....................................................................................................................................... 20
5.3
PORT-LANE
MAPPING............................................................................................................................ 20
6
FUNCTIONAL DESCRIPTION ........................................................................................................................ 21
6.1
PHYSICAL
LAYER
CIRCUIT .................................................................................................................. 21
6.1.1
RECEIVER DETECTION ................................................................................................................... 21
6.1.2
RECEIVER SIGNAL DETECTION ..................................................................................................... 22
6.1.3
RECEIVER EQUALIZATION ............................................................................................................. 22
6.1.4
TRANSMITTER SWING ...................................................................................................................... 22
6.1.5
DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS .................................................................... 22
6.1.6
DRIVE AMPLITUDE .......................................................................................................................... 23
6.1.7
DRIVE DE-EMPHASIS ...................................................................................................................... 24
6.1.8
TRANSMITTER ELECTRICAL IDLE LATENCY ............................................................................... 24
6.2
DATA
LINK
LAYER
(DLL) ...................................................................................................................... 24
6.3
TRANSACTION
LAYER
RECEIVE
BLOCK
(TLP
DECAPSULATION) .............................................. 25
6.4
ROUTING .................................................................................................................................................. 25
6.5
TC/VC
MAPPING ...................................................................................................................................... 25
6.6
QUEUE ....................................................................................................................................................... 26
6.6.1
PH ....................................................................................................................................................... 26
6.6.2
PD ....................................................................................................................................................... 26
6.6.3
NPHD ................................................................................................................................................. 26
6.6.4
CPLH .................................................................................................................................................. 26
6.6.5
CPLD .................................................................................................................................................. 26
6.7
TRANSACTION
ORDERING ................................................................................................................... 27
6.8
PORT
ARBITRATION .............................................................................................................................. 27
6.9
VC
ARBITRATION ................................................................................................................................... 28
6.10
FLOW
CONTROL ..................................................................................................................................... 28
6.11
TRANSATION
LAYER
TRANSMIT
BLOCK
(TLP
ENCAPSULATION) ............................................. 28
7
EEPROM INTERFACE AND SYSTEM MANAGEMENT/I2C BUS .............................................................. 29
7.1
EEPROM
INTERFACE ............................................................................................................................. 29
7.1.1
AUTO MODE EERPOM ACCESS ..................................................................................................... 29
7.1.2
EEPROM MODE AT RESET .............................................................................................................. 29
7.1.3
EEPROM SPACE ADDRESS MAP .................................................................................................... 29
7.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS .......................................... 32
7.2
SMBUS
INTERFACE ................................................................................................................................ 47
7.2.1
SMBUS BLOCK WRITE ..................................................................................................................... 48
7.2.2
SMBUS BLOCK READ ....................................................................................................................... 50
7.2.3
CSR READ, USING SMBUS BLOCK READ – BLOCK WRITE PROCESS CALL ............................ 52
7.3
I
2
C
SLAVE
INTERFACE ........................................................................................................................... 53
7.3.1
I
2
C REGISTER WRITE ACCESS ........................................................................................................ 54
7.3.2
I
2
C REGISTER READ ACCESS .......................................................................................................... 56
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