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Verilog and SystemVerilog
Gotchas
101
Common CodingErrors and
How
to
Avoid
Them
Stuart Sutherland
Don Mills
Verilog
and
SystemVerilog
Gotchas
101
Common
Coding
Errors
and
How
to
Avoid
Them
~
Springer
StuartSutherland
Sutherland
HDL,
Inc.
Tualatin, OR
USA
Don Mills
LCDM
Engineering
Chandler, AZ
USA
Libraryof CongressControl
Number:
2007926706
ISBN978-0-387-71714-2
Printedon acid-freepaper.
e-ISBN978-0-387-71715-9
© 2007SpringerScience+Business Media,LLC
All rights reserved. This work may not be translated or copied in whole or in part without
the writtenpermissionof the publisher(SpringerScience-BusinessMedia,LLC,233 Spring
Street,New York,NY 10013,USA),except for brief excerptsin connection with
reviews
or
scholarly analysis. Use in connection with any form of information storage and retrieval,
electronic adaptation, computer software, or by similar or dissimilar
methodology
now
know or hereafter developed is forbidden. The use in this publication of trade names,
trademarks, servicemarks and similarterms, even if they are not identifiedas such,is not to
be taken as an expression of opinion as to whether or not they are subject to proprietary
rights.
9 8 7 6 5
432
1
springer.com
Dedication
To
my wonderful
wife,
LeeAnn,
andmy
children,
Ammon,
Tamara,
Hannah,
Sethand
Samuel- thankyoufor yourpatienceduringthe manylonghoursand latenights
you toleratedwhilethis bookwas being
written.
StuSutherland
Portland,
Oregon
To
my wifeandsweetheart Geri
Jean,
and my
children,
Sara,
Kirsten,
Adam,
Alex,
Dillan,
Donnelle,
Grantand Gina-
thanks
to each
of
youfor thepatienceyou have
hadwithme as
I havedealtwith
debugging
many
of
thesegotchason
designs
overthe
years.
Don
Mills
Chandler,
Arizona
About
the
Authors
Mr.
Stuart
Sutherland
is a
member
of the
IEEE
1800
working
group that
oversees
both the
Verilog
and
System
Verilog
standards.
He has been
involved
with the
definition
of the
Veri
log
standard
since its
inception
in
1993,
and the
System
Verilog
standard
since work
began
in 200I. In
addition,
Stuart
is the
technical
editor of the official
IEEE
Verilog
and
SystemVerilog
Language
Reference
Manuals
(LRMs)
.
Stuart
is
an
independent
Verilog
consultant, specializing in
providing
comprehensive
expert
training
on the
Verilog
HDL,
System
Verilog
and
PLI.
Stuart
is a co-authorof the
books
"SystemVerilog for Design",
"Verilog
-2001
: A
Guide
to the New
Features
in the
Verilog
Hardware
Description
Language"
and
is the
author
of "The
Verilog
PLl
Handbook
", as well as the
popular
"Verilog
HDL
Quick
Reference
Guide"
and
"Verilog
PLl Quick
Reference
Guide"
. He has
alsoauthored a
number
of
technical
papers
on
Verilog
and
System
Verilog,
which
are
available
at www.sutherland-hdl.com/papers.
You
can
contact
Stuart
at
stuart@sutherland-hdl.com.
visitthe author
swebpage at
www.sutherland-hdl.com
Mr. Don
Mills
has been
involved
in ASIC
design
since
1986.
During
that
time,
he has
worked
on morethan 30
ASIC
projects.
Don started using
top-down
design
methodology
in
1991
(Synopsys
Design
Compiler
1.2)
. Don has
developed
and
implemented
top-down
ASIC
design
flows
at
several
companies.
His specialty is integrating tools and
automating
the
flow
. Don
works
for
Microchip
Technology
Inc. as an
internal
System
Verilog
and
Verilog
consultant.
Don is a
member
of the
IEEE
Veri
log and
System
Veri
log
committees
that are
working
on
language
issues
and
enhancements
. Don has
authored
and co-authored
numerous
papers,
such as
"SystemVerilog
Assertions
are for
Design
Engineers
Too!"
and
"RTL
Coding
Styles
that
Yield
Simulation
and
Synthesis
Mismatches".
Copies
of
these
papers
can be
found
at
www.lcdm-eng
.com
.Mr
. Mills can be
reached
at
mills@lcdm-eng
.comor don.mills@microchip.com.
visitthe author
swebpage at www.lcdm-eng.com
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