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OMAP L138 资料
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OMAP-L138芯片资料,低功耗,C6x DSP+ARM926双核,使用于低功耗手持设备开发。
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OMAP-L138
www.ti.com
SPRS586D–JUNE 2009– REVISED OCTOBER 2011
OMAP-L138 C6-Integra™ DSP+ARM® Processor
Check for Samples: OMAP-L138
1 OMAP-L138 C6-Integra™ DSP+ARM® Processor
1.1 Features
12
– Bit-Field Extract, Set, Clear
• Highlights
– Normalization, Saturation, Bit-Counting
– Dual Core SoC
– Compact 16-Bit Instructions
• 375/456-MHz ARM926EJ-S™ RISC MPU
• C674x Two Level Cache Memory Architecture
• 375/456-MHz C674x Fixed/Floating-Point
VLIW DSP – 32K-Byte L1P Program RAM/Cache
– Supports TI’s Basic Secure Boot – 32K-Byte L1D Data RAM/Cache
– Enhanced Direct-Memory-Access Controller – 256K-Byte L2 Unified Mapped RAM/Cache
(EDMA3)
– Flexible RAM/Cache Partition (L1 and L2)
– Serial ATA (SATA) Controller
• Enhanced Direct-Memory-Access Controller 3
– DDR2/Mobile DDR Memory Controller (EDMA3):
– Two Multimedia Card (MMC)/Secure Digital – 2 Channel Controllers
(SD) Card Interface
– 3 Transfer Controllers
– LCD Controller
– 64 Independent DMA Channels
– Video Port Interface (VPIF)
– 16 Quick DMA Channels
– 10/100 Mb/s Ethernet MAC (EMAC)
– Programmable Transfer Burst Size
– Programmable Real-Time Unit Subsystem
• TMS320C674x Floating-Point VLIW DSP Core
– Three Configurable UART Modules
– Load-Store Architecture With Non-Aligned
– USB 1.1 OHCI (Host) With Integrated PHY Support
– USB 2.0 OTG Port With Integrated PHY – 64 General-Purpose Registers (32 Bit)
– One Multichannel Audio Serial Port – Six ALU (32-/40-Bit) Functional Units
– Two Multichannel Buffered Serial Ports • Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
• Dual Core SoC
Precision/64-Bit) Floating Point
– 375/456-MHz ARM926EJ-S™ RISC MPU
• Supports up to Four SP Additions Per
– 375/456-MHz C674x Fixed/Floating-Point
Clock, Four DP Additions Every 2 Clocks
VLIW DSP
• Supports up to Two Floating Point (SP or
• ARM926EJ-S Core
DP) Reciprocal Approximation (RCPxP)
– 32-Bit and 16-Bit (Thumb®) Instructions
and Square-Root Reciprocal
– DSP Instruction Extensions
Approximation (RSQRxP) Operations Per
– Single Cycle MAC
Cycle
– ARM® Jazelle® Technology
– Two Multiply Functional Units
– EmbeddedICE-RT™ for Real-Time Debug
• Mixed-Precision IEEE Floating Point
• ARM9 Memory Architecture
Multiply Supported up to:
– 16K-Byte Instruction Cache
– 2 SP x SP → SP Per Clock
– 16K-Byte Data Cache
– 2 SP x SP → DP Every Two Clocks
– 8K-Byte RAM (Vector Table)
– 2 SP x DP → DP Every Three Clocks
– 64K-Byte ROM
– 2 DP x DP → DP Every Four Clocks
• C674x™ Instruction Set Features
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
– Superset of the C67x+™ and C64x+™ ISAs
Multiplies, or Eight 8 x 8-Bit Multiplies per
– Up to 3648/2746 C674x MIPS/MFLOPS
Clock Cycle, and Complex Multiples
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– Instruction Packing Reduces Code Size
– 8-Bit Overflow Protection
– All Instructions Conditional
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OMAP-L138
SPRS586D–JUNE 2009– REVISED OCTOBER 2011
www.ti.com
–
Hardware Support for Modulo Loop • USB 1.1 OHCI (Host) With Integrated PHY
Operation (USB1)
– Protected Mode Operation • USB 2.0 OTG Port With Integrated PHY (USB0)
– Exceptions Support for Error Detection and – USB 2.0 High-/Full-Speed Client
Program Redirection
– USB 2.0 High-/Full-/Low-Speed Host
• Software Support
– End Point 0 (Control)
– TI DSP/BIOS™
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
– Chip Support Library and DSP Library ISOC) Rx and Tx
• 128K-Byte RAM Shared Memory • One Multichannel Audio Serial Port:
• 1.8V or 3.3V LVCMOS IOs (except for USB and – Two Clock Zones and 16 Serial Data Pins
DDR2 interfaces)
– Supports TDM, I2S, and Similar Formats
• Two External Memory Interfaces:
– DIT-Capable
– EMIFA
– FIFO buffers for Transmit and Receive
• NOR (8-/16-Bit-Wide Data)
• Two Multichannel Buffered Serial Ports:
• NAND (8-/16-Bit-Wide Data)
– Supports TDM, I2S, and Similar Formats
• 16-Bit SDRAM With 128 MB Address
– AC97 Audio Codec Interface
Space
– Telecom Interfaces (ST-Bus, H100)
– DDR2/Mobile DDR Memory Controller
– 128-channel TDM
• 16-Bit DDR2 SDRAM With 512 MB
– FIFO buffers for Transmit and Receive
Address Space or
• 10/100 Mb/s Ethernet MAC (EMAC):
• 16-Bit mDDR SDRAM With 256 MB
– IEEE 802.3 Compliant
Address Space
– MII Media Independent Interface
• Three Configurable 16550 type UART Modules:
– RMII Reduced Media Independent Interface
– With Modem Control Signals
– Management Data I/O (MDIO) Module
– 16-byte FIFO
• Video Port Interface (VPIF):
– 16x or 13x Oversampling Option
– Two 8-bit SD (BT.656), Single 16-bit or Single
• LCD Controller
Raw (8-/10-/12-bit) Video Capture Channels
• Two Serial Peripheral Interfaces (SPI) Each
– Two 8-bit SD (BT.656), Single 16-bit Video
With Multiple Chip-Selects
Display Channels
• Two Multimedia Card (MMC)/Secure Digital (SD)
• Universal Parallel Port (uPP):
Card Interface with Secure Data I/O (SDIO)
– High-Speed Parallel Interface to FPGAs and
Interfaces
Data Converters
• Two Master/Slave Inter-Integrated Circuit (I
2
C
– Data Width on Each of Two Channels is 8- to
Bus™)
16-bit Inclusive
• One Host-Port Interface (HPI) With 16-Bit-Wide
– Single Data Rate or Dual Data Rate Transfers
Muxed Address/Data Bus For High Bandwidth
– Supports Multiple Interfaces with START,
• Programmable Real-Time Unit Subsystem
ENABLE and WAIT Controls
(PRUSS)
• Serial ATA (SATA) Controller:
– Two Independent Programmable Realtime
– Supports SATA I (1.5 Gbps) and SATA II (3.0
Unit (PRU) Cores
Gbps)
• 32-Bit Load/Store RISC architecture
– Supports all SATA Power Management
• 4K Byte instruction RAM per core
Features
• 512 Bytes data RAM per core
– Hardware-Assisted Native Command
• PRU Subsystem (PRUSS) can be disabled
Queueing (NCQ) for up to 32 Entries
via software to save power
– Supports Port Multiplier and
• Register 30 of each PRU is exported from
Command-Based Switching
the subsystem in addition to the normal
• Real-Time Clock With 32 KHz Oscillator and
R31 output of the PRU cores.
Separate Power Rail
– Standard power management mechanism
• Three 64-Bit General-Purpose Timers (Each
• Clock gating
Configurable as Two 32-Bit Timers)
• Entire subsystem under a single PSC
• One 64-bit General-Purpose/Watchdog Timer
clock gating domain
(Configurable as Two 32-bit General-Purpose
– Dedicated interrupt controller
Timers)
– Dedicated switched central resource
2 OMAP-L138 C6-Integra™ DSP+ARM® Processor Copyright © 2009–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): OMAP-L138
OMAP-L138
www.ti.com
SPRS586D–JUNE 2009– REVISED OCTOBER 2011
• Two Enhanced Pulse Width Modulators – Configurable as 3 Capture Inputs or 3
(eHRPWM): Auxiliary Pulse Width Modulator (APWM)
outputs
– Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control – Single Shot Capture of up to Four Event
Time-Stamps
– 6 Single Edge, 6 Dual Edge Symmetric or 3
Dual Edge Asymmetric Outputs • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZCE Suffix], 0.65-mm Ball Pitch
– Dead-Band Generation
• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
– PWM Chopping by High-Frequency Carrier
[ZWT Suffix], 0.80-mm Ball Pitch
– Trip Zone Input
• Commercial, Extended or Industrial
• Three 32-Bit Enhanced Capture Modules
Temperature
(eCAP):
Copyright © 2009–2011, Texas Instruments Incorporated OMAP-L138 C6-Integra™ DSP+ARM® Processor 3
Submit Documentation Feedback
Product Folder Link(s): OMAP-L138
OMAP-L138
SPRS586D–JUNE 2009– REVISED OCTOBER 2011
www.ti.com
1.2 Description
The OMAP-L138 C6-Integra™ DSP+ARM® processor is a low-power applications processor based on an
ARM926EJ-S™ and a C674x DSP core. It provides significantly lower power than other members of the
TMS320C6000™ platform of DSPs.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an
ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and
16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core
also has a 8KB RAM (Vector Table) and 64KB ROM.
The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a
32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The
Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and
data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM
shared memory is available for use by other hosts without affecting DSP performance.
For security enabled devices, TI’s Basic Secure Boot allows users to protect proprietary intellectual
property and prevents external entities from modifying user-developed algorithms. By starting from a
hardware-based “root-of-trust”, the secure boot flow guarantees a known good starting point for code
execution. By default, the JTAG port is locked down to prevent emulation and debug attacks but can be
enabled during the secure boot process during application development. The boot modules themselves
are encrypted while sitting in external non-volatile memory, such as flash or EEPROM, and are decrypted
and authenticated when loaded during secure boot. This protects the users’ IP and enables them to
securely set up the system and begin device operation with known, trusted code. Basic Secure Boot
utilizes either SHA-1 or SHA-256, and AES-128 for boot image validation. It also uses AES-128 for boot
image encryption. The secure boot flow employs a multi-layer encryption scheme which not only protects
the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit
device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random
number generator, is used to protect user encryption keys. When an update is needed, the customer
creates a new encrypted image using its encryption keys. Then the device can acquire the image via an
external interface, such as Ethernet, and overwrite the existing code. For more details on the supported
security features or TI’s Basic Secure Boot, refer to the TMS320C674x/OMAP-L1x Processor Security
User’s Guide (SPRUGQ9).
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C)
Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two
multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip
selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a
configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output
(GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three
4 OMAP-L138 C6-Integra™ DSP+ARM® Processor Copyright © 2009–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): OMAP-L138
OMAP-L138
www.ti.com
SPRS586D–JUNE 2009– REVISED OCTOBER 2011
UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator
(eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured
as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory
interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or
peripherals, and a higher speed DDR2/Mobile DDR controller.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is
available for PHY configuration. The EMAC supports both MII and RMII interfaces.
The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller
supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).
The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters,
FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on
each of two channels. Single-data rate and double-data rate transfers are supported as well as START,
ENABLE and WAIT signals to provide control for a variety of data converters.
A Video Port Interface (VPIF) is included providing a flexible video input/output port.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The device has a complete set of development tools for the ARM and DSP. These include C compilers, a
DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface
for visibility into source code execution.
Copyright © 2009–2011, Texas Instruments Incorporated OMAP-L138 C6-Integra™ DSP+ARM® Processor 5
Submit Documentation Feedback
Product Folder Link(s): OMAP-L138
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