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FUJITSU SPI接口存储芯片MB85RS16 系列英文资料.pdf
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FUJITSU SPI接口存储芯片MB85RS16 系列英文资料pdf,FUJITSU SPI接口存储芯片MB85RS16 系列英文资料
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FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.1
Memory FRAM
16 K (2 K × 8) Bit SPI
MB85RS16
■ DESCRIPTION
MB85RS16 is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 2,048 words ×
8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile
memory cells.
MB85RS16 adopts the Serial Peripheral Interface (SPI).
The MB85RS16 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS16 can be used for 10
12
read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E
2
PROM.
MB85RS16 does not take long time to write data unlike Flash memories nor E
2
PROM, and MB85RS16 takes
no wait time.
■ FEATURES
• Bit configuration : 2,048 words × 8 bits
• Serial Peripheral Interface : SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
• Operating frequency : 20 MHz (Max)
• High endurance : 1 trillion Read/Writes per bit
• Data retention : 10 years (+85 °C)
• Operating power supply voltage : 2.7 V to 3.6 V
• Low power consumption : Operating power supply current 1.5(TBD)mA (Typ@20 MHz)
Standby current 5 μA(TBD) (Typ)
• Operation ambient temperature range : − 40 °C to +85 °C
• Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant
DS501-00014-0v01-E
MB85RS16
2 DS501-00014-0v01-E
■ PIN ASSIGNMENT
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name Functional description
1CS
Chip Select pin
This is an input pin to make chips select. When CS
is the “H” level, device is in deselect
(standby) status as long as device is not write status internally, and SO becomes High-
Z. Inputs from other pins are ignored at this time. When CS
is the “L” level, device is in
select (active) status. CS
has to be the “L” level before inputting op-code. The Chip Se-
lect pin is pulled up internally to the VDD pin.
3WP
Write Protect pin
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP
and WPEN. See “■WRITING
PROTECT” for detail.
7HOLD
Hold pin
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD
is the “L” level, hold operation is activated, SO becomes High-Z, SCK and SI be-
come don’t care. While the hold operation, CS
has to be retained the “L” level.
6SCK
Serial Clock pin
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
5SI
Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data.
2SO
Serial Data Output pin
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
8 VDD Supply Voltage pin
4 GND Ground pin
GNDSI
SO
VDD
SCK
WP
CS
HOLD
8
7
6
54
3
2
1
(TOP VIEW)
(FPT-8P-M02)
MB85RS16
DS501-00014-0v01-E 3
■ BLOCK DIAGRAM
SCK
SO
SI
Serial-Parallel Converter
FRAM Cell Array
2,048 ✕ 8
Column Decoder/Sense Amp/
Write Amp
FRAM
Status Register
Data Register
Parallel-Serial Converter
Control Circuit
Address Counter
Row Decoder
CS
WP
HOLD
MB85RS16
4 DS501-00014-0v01-E
■ SPI MODE
MB85RS16 corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) .
SCK
SI
CS
SCK
SI
CS
76543210
76543210
MSB LSB
MSB LSB
SPI Mode 0
SPI Mode 3
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