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Clock Domain Crossing (CDC) Design & Verification
Techniques Using SystemVerilog
Clifford E. Cummings
Sunburst Design, Inc.
cliffc@sunburst-design.com
ABSTRACT
Important design considerations require that multi-clock designs be carefully constructed at
Clock Domain Crossing (CDC) boundaries. This paper details some of the latest strategies and
best known methods to address passing of one and multiple signals across a CDC boundary.
Included in the paper are techniques related to CDC verification and an interesting 2-deep FIFO
design for passing multiple control signals between clock domains. Although the design methods
described in the paper can be generally implemented using any HDL, the examples are shown
using efficient SystemVerilog techniques.
SNUG Boston 2008 Clock Domain Crossing (CDC) Design & Verification
Techniques Using SystemVerilog
2
Table of Contents
1.0 Introduction........................................................................................................................... 6
2.0 Metastability ......................................................................................................................... 6
2.1 Why is metastability a problem? .......................................................................................... 7
3.0 Synchronizers........................................................................................................................ 8
3.1 Two synchronization scenarios............................................................................................. 8
3.2 Two flip-flop synchronizer ...................................................................................................8
3.3 MTBF - mean time before failure......................................................................................... 9
3.4 Three flip-flop synchronizer............................................................................................... 10
3.5 Synchronizing signals from the sending clock domain ...................................................... 10
3.6 Synchronizing signals into the receiving clock domain ..................................................... 11
4.0 Synchronizing fast signals into slow clock domains .......................................................... 13
4.1 Requirement for reliable signal passing between clock domains....................................... 13
4.1.1 The "three edge" requirement.......................................................................................... 13
4.2 Problem - passing a fast CDC pulse ................................................................................... 14
4.3 Problem - sampling a long CDC pulse - but not long enough!........................................... 15
4.4 Open-loop solution - sampling signals with synchronizers................................................ 16
4.5 Closed loop solution - sampling signals with synchronizers.............................................. 17
5.0 Passing multiple signals between clock domains ............................................................... 18
5.1 Multi-bit CDC strategies.....................................................................................................18
5.2 Multi-bit signal consolidation............................................................................................. 18
5.3 Problem - Two simultaneously required control signals.................................................... 19
5.3.1 Solution - Consolidation.................................................................................................. 20
5.4 Problem - Two phase-shifted sequencing control signals. ................................................. 21
5.4.1 Solution - consolidation and an extra flip-flop................................................................ 22
5.5 Problem - Multiple CDC signals ........................................................................................ 23
5.5.1 Solutions for passing multiple CDC signals.................................................................... 23
5.6 Multi-Cycle Path (MCP) formulation................................................................................. 24
5.6.1 MCP formulation using a synchronized enable pulse..................................................... 25
5.6.2 Closed-loop - MCP formulation with feedback .............................................................. 27
5.6.3 Closed-loop - MCP formulation with acknowledge feedback ........................................ 28
5.7 Synchronizing counters.......................................................................................................29
5.7.1 Binary counters................................................................................................................ 29
5.7.2 Gray codes....................................................................................................................... 30
5.7.3 Gray-to-binary conversion............................................................................................... 30
5.7.4 Binary-to-gray conversion............................................................................................... 31
5.7.5 Gray code counter style #1.............................................................................................. 32
5.7.6 Gray code counter style #2.............................................................................................. 33
5.8 Additional multi-bit CDC techniques................................................................................. 34
5.8.1 Multi-bit CDC signal passing using asynchronous FIFOS ............................................. 34
5.8.2 Multi-bit CDC signal passing using 1-deep / 2-register FIFO synchronizer .................. 35
6.0 Naming conventions & design partitioning........................................................................ 36
6.1 Clock & signal naming conventions................................................................................... 36
6.1.1 Multi-clock / multi-source modules with no naming convention .................................. 37
SNUG Boston 2008 Clock Domain Crossing (CDC) Design & Verification
Techniques Using SystemVerilog
3
6.2 Timing verification for each clock domain......................................................................... 37
6.3 Clock oriented design partitioning...................................................................................... 37
6.3.1 Timing analysis of clock-partitioned modules ................................................................ 39
6.4 Partitioning with MCP formulations................................................................................... 40
7.0 Multi-clock gate-level simulation issues ............................................................................ 41
7.1 Synchronizer gate-level CDC simulation issue .................................................................. 41
7.2 Strategies to remove X-propagation from gate-level simulations ...................................... 41
7.2.1 Simulator command to turn off timing checks................................................................ 42
7.2.2 Change flip-flop setup and hold times to 0 ..................................................................... 42
7.2.3 Copy and modify new flip-flop models........................................................................... 42
7.2.4 Synopsys set_annotated_check command....................................................................... 42
7.3 Additional strategies to remove X-propagation.................................................................. 43
7.3.1 Use multiple SDF files .................................................................................................... 43
7.3.2 Vendor synchronizer cell with supporting SDF generation tools ................................... 43
7.3.3 Vendors with built-in synchronizer support.................................................................... 44
7.4 Multiple SDF files for gate-level CDC simulations ........................................................... 44
7.5 Force synchronizer notifier inputs to a fixed value ............................................................ 44
7.6 ASIC & FPGA library cell synchronizers .......................................................................... 45
7.7 Simulation model with random delay insertion.................................................................. 46
8.0 Summary & conclusions..................................................................................................... 47
8.1 Recommended 1-bit CDC techniques................................................................................. 47
8.2 Recommended multi-bit CDC techniques .......................................................................... 48
8.3 Recommended naming conventions and design partitioning ............................................. 48
8.4 Recommended solutions to multi-clock gate-level CDC simulations................................ 48
9.0 Acknowledgements.............................................................................................................48
10.0 References........................................................................................................................... 48
11.0 Author & Contact Information ........................................................................................... 49
12.0 Appendix............................................................................................................................. 50
12.1 Common sync2 model - used by MCP formulation and FIFO synchronizer ..................... 50
12.2 MCP formulation with ready-acknowledge source code.................................................... 50
12.3 Multi-bit 1-deep / 2-register FIFO synchronizer source code ............................................ 55
SNUG Boston 2008 Clock Domain Crossing (CDC) Design & Verification
Techniques Using SystemVerilog
4
Table of Figures
Figure 1 - Asynchronous clocks and synchronization failure......................................................... 6
Figure 2 - Metastable bdat1 output propagating invalid data throughout the design.................. 7
Figure 3 - Two flip-flop synchronizer ............................................................................................ 9
Figure 4 - Primary contributing factors to short MTBF values.................................................... 10
Figure 5 - Three flip-flop synchronizer used in higher speed designs ......................................... 10
Figure 6 - Unregistered signals sent across a CDC boundary ...................................................... 11
Figure 7 - Registered signals sent across a CDC boundary.......................................................... 12
Figure 8 - Short CDC signal pulse missed during synchronization.............................................. 14
Figure 9 - Marginal CDC pulse that violates the destination setup and hold times ..................... 15
Figure 10 - Lengthened pulse to guarantee that the control signal will be sampled .................... 16
Figure 11 - Signal with feedback to acknowledge receipt............................................................ 17
Figure 12 - Problem - Passing multiple control signals between clock domains ......................... 19
Figure 13 - Solution - Consolidating control signals before passing between clock domains..... 20
Figure 14 - Problem - Passing sequential control signals between clock domains ...................... 21
Figure 15 - Solution - Logic to generate proper sequencing signals in the new clock domains .. 22
Figure 16 - Problem - Encoded control signals passed between clock domains.......................... 23
Figure 17 - Logic to pass a synchronized enable pulse between clock domains.......................... 24
Figure 18 - Synchronized pulse generation logic ......................................................................... 25
Figure 19 - Synchronized enable pulse generation logic and equivalent symbol......................... 26
Figure 20 - Multi-Cycle Path (MCP ) formulation toggle-pulse generation ................................ 26
Figure 21 - Multi-Cycle Path (MCP ) formulation toggle-pulse generation with acknowledge.. 27
Figure 22 - Multi-Cycle Path (MCP ) formulation toggle-pulse generation with ready-ack ....... 28
Figure 23 - Binary count values sampled in mid-transition.......................................................... 29
Figure 24 - 4-bit gray-to-binary conversion equations................................................................. 30
Figure 25 - 4-bit gray-to-binary conversion equations - 2nd method........................................... 31
Figure 26 - 4-bit binary-to-gray conversion equations................................................................. 31
Figure 27 - Gray code counter style #1 - only one gray code register.......................................... 32
Figure 28 - Gray code counter style #2 - binary register and gray code register ......................... 33
Figure 29 - 1-deep / 2-register FIFO synchronizer block diagram............................................... 35
Figure 30 - Design partitioned on clock boundaries..................................................................... 38
Figure 31 - Partitioned design with MCP formulation ................................................................. 40
Figure 32 - Synchronizer gate-level CDC simulation waveforms................................................ 41
Figure 33 - Sample ASIC & FPGA synchronizer cell for synthesis and simulation.................... 46
SNUG Boston 2008 Clock Domain Crossing (CDC) Design & Verification
Techniques Using SystemVerilog
5
Table of Examples
Example 1 - Non-working but conceptually correct gray-to-binary SystemVerilog model......... 30
Example 2 - Parameterized and correct gray-to-binary SystemVerilog model............................ 31
Example 3 - Parameterized binary-to-gray SystemVerilog model............................................... 32
Example 5 - Parameterized gray-code counter SystemVerilog model......................................... 33
Example 6 - Parameterized gray-code counter with binary counter............................................. 34
Example 7 - SystemVerilog model for ASIC & FPGA synchronizer cell ................................... 47
Example 8 - sync2.sv code............................................................................................................ 50
Example 9 - plsgen.sv code .......................................................................................................... 50
Example 10 - asend_fsm.sv code..................................................................................................51
Example 11 - back_fsm.sv code ...................................................................................................51
Example 12 - bmcp_recv.sv code................................................................................................. 52
Example 13 - mcp_blk.sv code..................................................................................................... 53
Example 14 - acmp_send.sv code................................................................................................. 54
Example 15 - wctl.sv code............................................................................................................ 55
Example 16 - cdc_syncfifo.sv code .............................................................................................. 55
Example 17 - Dual Port Ram code - dp_ram2.sv ......................................................................... 56
Example 18 - rctl.sv code ............................................................................................................. 56
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