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This reference manual defines the functionality of the MPC8309. The MPC8309 is a cost-effective, highly integrated communications processor that addresses the requirements of several networking applications, including residential gateways, modem/routers, industrial control, and test and measurement applications. The MPC8309 extends current PowerQUICC offerings, adding higher CPU performance, additional functionality, and faster interfaces, while addressing the requirements related to time-to-market, price, power consumption, and board real estate.
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MPC8309 PowerQUICC II Pro
Integrated Communications
Processor Reference Manual
MPC8309RM
Rev. 0
4/2011
Freescale, the Freescale logo, CodeWarrior, ColdFire, PowerQUICC,
StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.
Reg. U.S. Pat. & Tm. Off. CoreNet, QorIQ, QUICC Engine, and VortiQa are
trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. The Power Architecture
and Power.org word marks and the Power and Power.org logos and related
marks are trademarks and service marks licensed by Power.org. RapidIO is
a registered trademark of the RapidIO Trade Association. IEEE 1588,
1149.1, 802.3, and 754 are registered trademarks of the Institute of
Electrical and Electronics Engineers, Inc. (IEEE). This product is not
endorsed or approved by the IEEE.
© 2011 Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
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Semiconductor was negligent regarding the design or manufacture of the part.
Document Number: MPC8309RM
Rev. 0, 4/2011
How to Reach Us:
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MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 0
Freescale Semiconductor i
Contents
Paragraph
Number Title
Page
Number
About This Book
Organization....................................................................................................................xlix
Suggested Reading.............................................................................................................. li
Conventions ....................................................................................................................... lii
Signal Conventions............................................................................................................ lii
Acronyms and Abbreviations ........................................................................................... liii
Chapter 1
Overview
1.1 MPC8309 PowerQUICC II Pro Processor Overview...................................................... 1-1
1.2 Features............................................................................................................................ 1-2
1.3 MPC8309 Architecture Overview ................................................................................... 1-7
1.3.1 Power Architecture Core ............................................................................................. 1-7
1.3.2 QUICC Engine Block................................................................................................ 1-10
1.3.3 DDR2 Memory Controller......................................................................................... 1-14
1.3.4 PCI Bus Interface....................................................................................................... 1-14
1.3.5 I/O Sequencer ............................................................................................................ 1-15
1.3.6 Enhanced Local Bus Controller (eLBC).................................................................. 1-15
1.3.7 Integrated Programmable Interrupt Controller (IPIC)............................................... 1-17
1.3.8 Enhanced Secure Digital Host Controller (eSDHC).................................................. 1-17
1.3.9 Universal Serial Bus (USB) 2.0................................................................................. 1-18
1.3.10 FlexCAN Module ...................................................................................................... 1-19
1.3.11 Dual I
2
C Interfaces .................................................................................................... 1-20
1.3.12 DMA Engine 1........................................................................................................... 1-20
1.3.13 DMA Engine 2........................................................................................................... 1-21
1.3.14 Dual Universal Asynchronous Receiver/Transmitter (DUART)............................... 1-21
1.3.15 Serial Peripheral Interface (SPI)................................................................................ 1-22
1.3.16 System Timers ........................................................................................................... 1-22
1.3.17 Real Time Clock ........................................................................................................ 1-22
Chapter 2
Memory Map
2.1 Internal Memory Mapped Registers ................................................................................ 2-1
2.2 Accessing IMMR Memory from the Local Processor..................................................... 2-1
2.3 IMMR Address Map........................................................................................................ 2-1
MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 0
ii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Output Signal States During Reset ................................................................................ 3-19
Chapter 4
Reset, Clocking, and Initialization
4.1 External Signals ............................................................................................................... 4-1
4.1.1 Reset Signals................................................................................................................ 4-1
4.1.2 Clock Signals............................................................................................................... 4-2
4.2 Functional Description..................................................................................................... 4-4
4.2.1 Reset Operations.......................................................................................................... 4-4
4.2.2 Power-On Reset Flow.................................................................................................. 4-6
4.2.3 Hard Reset Flow .......................................................................................................... 4-7
4.3 Reset Configuration......................................................................................................... 4-8
4.3.1 Reset Configuration Signals ........................................................................................ 4-8
4.3.2 Reset Configuration Words........................................................................................ 4-10
4.3.3 Loading the Reset Configuration Words ................................................................... 4-17
4.4 Clocking ........................................................................................................................ 4-24
4.4.1 System Clock Domains.............................................................................................. 4-25
4.5 Memory Map/Register Definitions................................................................................ 4-27
4.5.1 Reset Configuration Register Descriptions................................................................ 4-27
4.5.2 Clock Configuration Registers................................................................................... 4-31
Chapter 5
System boot
5.1 Booting from On Chip ROM........................................................................................... 5-1
5.2 eSDHC Boot .................................................................................................................... 5-1
5.2.1 Overview...................................................................................................................... 5-2
5.2.2 Features........................................................................................................................ 5-2
5.2.3 SD/MMC Card Data Structure .................................................................................... 5-3
5.2.4 eSDHC Controller Initial Configuration...................................................................... 5-7
5.2.5 eSDHC Controller Boot Sequence .............................................................................. 5-7
5.2.6 eSDHC Boot Error Handling....................................................................................... 5-8
5.3 SPI Boot ROM.................................................................................................................5-9
5.3.1 Overview.................................................................................................................... 5-10
5.3.2 Features...................................................................................................................... 5-10
5.3.3 EEPROM Data Structure........................................................................................... 5-10
MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual, Rev. 0
Freescale Semiconductor iii
Contents
Paragraph
Number Title
Page
Number
5.3.4 SPI Controller Configuration..................................................................................... 5-13
Chapter 6
System Configuration
6.1 Introduction...................................................................................................................... 6-1
6.2 Local Memory Map Overview and Example .................................................................. 6-1
6.2.1 Address Translation and Mapping............................................................................... 6-3
6.2.2 Window into Configuration Space............................................................................... 6-3
6.2.3 Local Access Windows................................................................................................ 6-4
6.2.4 Local Access Register Descriptions ............................................................................ 6-6
6.2.5 Precedence of Local Access Windows ...................................................................... 6-14
6.2.6 Configuring Local Access Windows ......................................................................... 6-14
6.2.7 Distinguishing Local Access Windows from Other Mapping Functions.................. 6-14
6.2.8 Outbound Address Translation and Mapping Windows............................................ 6-15
6.2.9 Inbound Address Translation and Mapping Windows .............................................. 6-15
6.2.10 Internal Memory Map................................................................................................ 6-15
6.3 System Configuration .................................................................................................... 6-16
6.3.1 System Configuration Register Memory Map........................................................... 6-16
6.3.2 System Configuration Registers ................................................................................ 6-17
6.3.3 Multisite Muxing ....................................................................................................... 6-42
6.4 Software Watchdog Timer (WDT)................................................................................. 6-42
6.4.1 WDT Overview.......................................................................................................... 6-42
6.4.2 WDT Features............................................................................................................ 6-43
6.4.3 WDT Modes of Operation......................................................................................... 6-43
6.4.4 WDT Memory Map/Register Definition ................................................................... 6-44
6.4.5 Functional Description............................................................................................... 6-46
6.4.6 Initialization/Application Information (WDT Programming Guidelines)................. 6-49
6.5 Real Time Clock Module (RTC).................................................................................... 6-49
6.5.1 Overview.................................................................................................................... 6-49
6.5.2 Features...................................................................................................................... 6-50
6.5.3 Modes of Operation ................................................................................................... 6-50
6.5.4 External Signal Description....................................................................................... 6-50
6.5.5 RTC Memory Map/Register Definition..................................................................... 6-51
6.5.6 Functional Description............................................................................................... 6-55
6.5.7 RTC Initialization Sequence...................................................................................... 6-56
6.6 Periodic Interval Timer (PIT) ........................................................................................ 6-56
6.6.1 PIT Overview............................................................................................................. 6-56
6.6.2 PIT Features...............................................................................................................6-57
6.6.3 PIT Modes of Operation ............................................................................................ 6-57
6.6.4 PIT External Signal Description................................................................................ 6-57
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