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TMS320C55x DSP

Mnemonic Instruction Set

Reference Guide

Literature Number: SPRU374G

October 2002

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,

modifications, enhancements, improvements, and other changes to its products and services at

any time and to discontinue any product or service without notice. Customers should obtain the

latest relevant information before placing orders and should verify that such information is current

and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the

time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of

sale in accordance with TI’s standard warranty. Testing and other quality control techniques are

used to the extent TI deems necessary to support this warranty. Except where mandated by

government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are

responsible for their products and applications using TI components. To minimize the risks

associated with customer products and applications, customers should provide adequate design

and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any

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Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

Related Documentation From Texas Instruments

The following books describe the C55x devices and related support tools. To

obtain a copy of any of these TI documents, call the Texas Instruments

Literature Response Center at (800) 477-8924. When ordering, please identify

the book by its title and literature number.

TMS320C55x Technical Overview (SPRU393). This overview is an

introduction to the TMS320C55x digital signal processor (DSP). The

TMS320C55x is the latest generation of fixed-point DSPs in the

TMS320C5000 DSP platform. Like the previous generations, this

processor is optimized for high performance and low-power operation.

This book describes the CPU architecture, low-power enhancements,

and embedded emulation features of the TMS320C55x.

TMS320C55x DSP CPU Reference Guide (literature number SPRU371)

describes the architecture, registers, and operation of the CPU for the

TMS320C55x digital signal processors (DSPs).

TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature

number SPRU375) describes the algebraic instructions individually. It

also includes a summary of the instruction set, a list of the instruction

opcodes, and a cross-reference to the mnemonic instruction set.

TMS320C55x Programmer’s Guide (literature number SPRU376) describes

ways to optimize C and assembly code for the TMS320C55x DSPs and

explains how to write code that uses special features and instructions of

the DSP.

TMS320C55x Optimizing C Compiler User’s Guide (literature number

SPRU281) describes the TMS320C55x C Compiler. This C compiler

accepts ANSI standard C source code and produces assembly language

source code for TMS320C55x devices.

TMS320C55x Assembly Language Tools User’s Guide (literature number

SPRU280) describes the assembly language tools (assembler, linker,

and other tools used to develop assembly language code), assembler

directives, macros, common object file format, and symbolic debugging

directives for TMS320C55x devices.

Trademarks

TMS320, TMS320C54x, TMS320C55x, C54x, and C55x are trademarks of

Texas Instruments.

Related Documentation From Texas Instruments / Trademarks

Contents

1 Terms, Symbols, and Abbreviations 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lists and defines the terms, symbols, and abbreviations used in the TMS320C55x DSP

mnemonic instruction set summary and in the individual instruction descriptions.

1.1 Instruction Set Terms, Symbols, and Abbreviations 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Instruction Set Conditional (cond) Fields 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Affect of Status Bits 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 Accumulator Overflow Status Bit (ACOVx) 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.2 C54CM Status Bit 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.3 CARRY Status Bit 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.4 FRCT Status Bit 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.5 INTM Status Bit 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.6 M40 Status Bit 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.7 RDM Status Bit 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.8 SATA Status Bit 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.9 SATD Status Bit 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.10 SMUL Status Bit 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.11 SXMD Status Bit 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.12 Test Control Status Bit (TCx) 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Instruction Set Notes and Rules 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 Notes 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.2 Rules 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Nonrepeatable Instructions 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Parallelism Features and Rules 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the parallelism features and rules of the TMS320C55x DSP mnemonic instruction set.

2.1 Parallelism Features 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Parallelism Basics 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Resource Conflicts 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Operators 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Address Generation Units 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Buses 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Soft-Dual Parallelism 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Soft-Dual Parallelism of MAR Instructions 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Execute Conditionally Instructions 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Other Exceptions 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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