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The DM9161A is a physical layer, single-chip, and low power transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media Independent Interface (MII), the DM9161A connects to the Medium Access Control (MAC) layer, ensuring a high inter operability from different vendors.
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DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
1 Final
Version: DM9161A-DS-F01
October 16, 2009
DAVICOM Semiconductor, Inc.
DM9161A
10/100 Mbps Fast Ethernet
Physical Layer Single Chip Transceiver
DATA SHEET
Final
Version: DM9161A-DS-F01
October 16, 2009

DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 2
Version: DM9161A-DS-F01
October 16, 2009
Table of Contents
1. General Description...................................................................3
2. Features ....................................................................................3
3. Block Diagram ...........................................................................4
4. Pin Configuration: ......................................................................5
5. Pin Description ..........................................................................6
5.1 Normal MII Interface, 21 pins ..................................................6
5.2 Media Interface, 4 pins ............................................................8
5.3 LED Interface, 3 pins ...............................................................8
5.4 Mode, 2 pins ............................................................................8
5.5 Bias and Clock, 4 pins.............................................................9
5.6 Power, 13 pins.........................................................................9
5.7 Table A (Media Type Selection) ..............................................9
5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI
(7-Wired) Mode .................................................................. 10
6. LED Configuration ...................................................................11
6.1 LED Functional Description…………….………….....………..12
7. Functional Description .............................................................13
7.1 MII interface...........................................................................13
7.2 100Base-TX Operation..........................................................15
7.2.1 100Base-TX Transmit.........................................................15
7.2.1.1 4B5B Encoder .................................................................16
7.2.1.2 Scrambler ...................................................................... .16
7.2.1.3 Parallel to Serial Converter..............................................16
7.2.1.4 NRZ to NRZI Encoder .....................................................16
7.2.1.5 MLT-3 Converter .............................................................16
7.2.1.6 MLT-3 Driver....................................................................16
7.2.1.7 4B5B Code Group ...........................................................17
7.2.2 100Base-TX Receiver ........................................................18
7.2.2.1 Signal Detect ...................................................................18
7.2.2.2 Adaptive Equalizer...........................................................18
7.2.2.3 MLT-3 to NRZI Decoder ..................................................18
7.2.2.4 Clock Recovery Module...................................................18
7.2.2.5 NRZI to NRZ....................................................................18
7.2.2.6 Serial to Parallel ..............................................................18
7.2.2.7 Descrambler ....................................................................18
7.2.2.8 Code Group Alignment ....................................................18
7.2.2.9 4B5B Decoder .................................................................18
7.2.3 10Base-T Operation ...........................................................18
7.2.4 Collision Detection..............................................................19
7.2.5 Carrier Sense .....................................................................19
7.2.6 Auto-Negotiation.................................................................19
7.2.7 MII Serial Management ......................................................20
7.2.8 Serial Management Interface .............................................20
7.2.9 Management Interface – Read Frame
Structure ..............................................................................20
7.2.10 Management Interface – Write Frame Structure ..............20
7.2.11 Power Reduced Mode ......................................................21
7.2.12 Power Down Mode ...........................................................21
7.2.13 Reduced Transmit Power Mode.......................................21
7.2.14 Feedback Vout and Vin for 5V……………………...…..….21
7.3 HP Auto-MDIX Functional Description.........................................22
8. MII Register Description ..........................................................23
8.1 Basic Mode Control Register (BMCR) - 00............................24
8.2 Basic Mode Status Register (BMSR) - 01 .............................25
8.3 PHY ID Identifier Register #1 (PHYIDR1) - 02 ......................26
8.4 PHY ID Identifier Register #2 (PHYIDR2) - 03 ......................26
8.5 Auto-negotiation Advertisement Register (ANAR)
- 04 ......................................................................................27
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 0528
8.7 Auto-negotiation Expansion Register (ANER)
- 06 ......................................................................................29
8.8 DAVICOM Specified Configuration Register (DSCR) –16.....29
8.9 DAVICOM Specified Configuration and Status Register
(DSCSR) - 17 ......................................................................31
8.10 10Base-T Configuration / Status (10BTCSR) - 18...............32
8.11 DAVICOM Specified Interrupt Register - 21 ........................32
8.12 DAVICOM Specified Receive Error Counter Register (RECR) -
22.........................................................................................33
8.13 DAVICOM Specified Disconnect Counter Register (DISCR) -
23.........................................................................................33
8.14 DAVICOM Hardware Reset Latch State
Register (RLSR) - 24 ............................................................34
9. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings( 25°C ) ........................................35
9.2 Operating Conditions .............................................................35
9.3 DC Electrical Characteristics .................................................36
9.4 AC Electrical Characteristics & Timing
Waveform .............................................................................. 36
9.4.1 TP Interface ........................................................................36
9.4.2 Oscillator/Crystal Timing.....................................................36
9.4.3 MDC/MDIO Timing .............................................................37
9.4.4 MDIO Timing when OUTPUT by STA ................................37
9.4.5 MDIO Timing when OUTPUT by DM9161A .......................37
9.4.6 100Base-TX Transmit Timing Parameters .........................38
9.4.7 100Base-TX Transmit Timing Diagram ..............................38
9.4.8 100Base-TX Receive Timing Parameters ..........................38
9.4.9 MII 100Base-TX Receive Timing Diagram .........................39
9.4.10 MII 10Base-T Nibble Transmit Timing Parameters ..........39
9.4.11 MII 10Base-T Nibble Transmit Timing
Diagram..........................................................................39
9.4.12 MII 10Base-T Receive Nibble Timing Parameters .......... 40
9.4.13 MII 10Base-T Receive Nibble Timing
Diagram..........................................................................40
9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters40
9.4.15 Auto-negotiation and Fast Link Pulse Timing Diagram ....41
9.4.16 RMII Receive Timing Diagram..........................................41
9.4.17 RMII Transmit Timing Diagram.........................................41
9.4.18 RMII Timing Diagram........................................................42
9.4.19 RMII Timing Parameter ....................................................42
9.4.20 Magnetics Selection Guide…………………………………43
10. Package Information..............................................................44
11.Order Information....................................................................45

DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
3 Final
Version: DM9161A-DS-F01
October 16, 2009
1. General Description
The DM9161A is a physical layer, single-chip, and low power transceiver for 100BASE-TX and 10BASE-T
operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable
(UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media
Independent Interface (MII), the DM9161A connects to the Medium Access Control (MAC) layer, ensuring a high
inter operability from different vendors.
TheDM9161A uses a low power and high performance advanced CMOS process. It contains the entire physical
layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS),
Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX
Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9161A provides a strong
support for the auto-negotiation function, utilizing automatic media speed and protocol selection. Furthermore, due
to the built-in wave shaping filter, the DM9161A needs no external filter to transport signals to the media in
100BASE-TX or 10BASE-T Ethernet operation.
2. Features
Fully comply with IEEE 802.3 / IEEE 802.3u 10Base-T/
100Base-TX, ANSI X3T12 TP-PMD 1995 standard
Support MDI/MDI-X auto crossover function
(Auto-MDI)
Support Auto-Negotiation function, compliant with IEEE
802.3u
Fully integrated Physical layer transceiver On-chip
filtering with direct interface to magnetic transformer
Selectable repeater or node mode
Selectable MII or RMII (Reduced MII) mode for
100Base-TX and 10Base-TX. Selectable MII or GPSI
(7-Wired) mode for 10Base-T
Selectable full-duplex or half-duplex operation
MII management interface with maskable interrupt
output capability
Provide Loopback mode for easy system
diagnostics
LED status outputs indicate Link/ Activity, Speed10/100
and Full-duplex/Collision. Support Dual-LED optional
control
Single low power Supply of 3.3V with an advanced
CMOS technology
Very Low Power consumption modes:
● Power Reduced mode (cable detection)
● Power Down mode
● Selectable TX drivers for 1:1 or 1.25:1 transformers
for additional power reduction. 1: 1 transformers only
when HP Auto-MDIX Enable .
Compatible with 3.3V and 5.0V tolerant I/Os
48-pin LQFP

DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 4
Version: DM9161A-DS-F01
October 16, 2009
3. Block Diagram
MII
Signals
MII
Interface/
Control
4B/5B
Encoder
4B/5B
Decoder
Register
Code-
group
Alignment
Descrambler
Serial to
Parallel
NRZI
to
NRZ
RX
CRM
MLT-3 to
NRZI
Adaptive
EQ
Digital
Logic
Scrambler
Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3
MLT-3
Driver
Rise/Fall
Time
CTL
TX CGM
LED
Driver
Collision
Detection
Carrier
Sense
Auto-
Negotiation
10BASE-T
Module
RX
TX
125M CLK
25M CLK
LED1-4#25M OSCI
RXI+/-
RXI+/-
10TXD+/-
100TXD+/-
AutoMDIX

DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5 Final
Version: DM9161A-DS-F01
October 16, 2009
4. Pin Configuration:
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
AVDDR
AVDDT
RX+
TX-
RX-
AGND
AGND
TX+
AVDDR
PWRDWN
LED0/OP0
LED1/OP1
RXDV/TESTMODE
RXER/RXD[4]/RPTR
DISMDIX
DVDD
RESET#
XT2
XT1
DGND
NC
AGND
BGRESG
BGRES
13
14
15
16
17
18
19
20
21
22
23
24
TXD[1]
LED2/OP2
CABLESTS/LINKSTS
DGND
TXER/TXD[4]
TXD[3]
TXD[2]
TXEN
TXCLK/ISOLATE
DVDD
TXD[0]
MDC
35
36
34
33
32
31
30
29
28
27
26
25
MDIO
RXD[0]/PHYAD[0]
RXD[2]/PHYAD[2]
RXD[3]/PHYAD[3]
RXD[1]/PHYAD[1]
DVDD
LEDMODE
MDINTR#
RXCLK/10BTSER
DGND
CRS/PHYAD[4]
COL/RMII
DM9161A
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