LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
ENTITY multplier2 is
generic(M: integer:=8 );
port( dataA: IN STD_LOGIC_VECTOR(M-1 DOWNTO 0);
dataB: IN STD_LOGIC_VECTOR(M-1 DOWNTO 0);
result: out std_logic_vector(M+M-1 DOWNTO 0));
END multplier2 ;
ARCHITECTURE BEH OF multplier2 is
begin
inset_mult: process(dataA,dataB)
variable dataA_temp,dataB_temp,temp: std_logic_vector(M-1 DOWNTO 0);
variable count: integer;
begin
dataA_temp := dataA;
dataB_temp := dataB;
temp:="00000000";
count:=0;
while count<M-1 LOOP
if ( dataA(count)='1') then
temp:= temp+ dataB_temp;
end if;
dataA_temp := temp(0) & dataA_temp(M-1 DOWNTO 1);
temp := '0' & temp(M-1 downto 1);
count := count + 1;
end loop;
result<=temp & dataA_temp;
END process inset_mult;
end architecture BEH;
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