AD9361的datasheet_AD9361datasheet

AD9361

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RF Agile Transceiver

Data Sheet

AD9361

Rev. F Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs

TX band: 47 MHz to 6.0 GHz

RX band: 70 MHz to 6.0 GHz

Supports TDD and FDD operation

Tunable channel bandwidth: <200 kHz to 56 MHz

Dual receivers: 6 differential or 12 single-ended inputs

Superior receiver sensitivity with a noise figure of 2 dB at

800 MHz LO

RX gain control

Real-time monitor and control signals for manual gain

Independent automatic gain control

Dual transmitters: 4 differential outputs

Highly linear broadband transmitter

TX EVM: ≤−40 dB

TX noise: ≤−157 dBm/Hz noise floor

TX monitor: ≥66 dB dynamic range with 1 dB accuracy

Integrated fractional-N synthesizers

2.4 Hz maximum local oscillator (LO) step size

Multichip synchronization

CMOS/LVDS digital interface

APPLICATIONS

Point to point communication systems

Femtocell/picocell/microcell base stations

General-purpose radio systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD9361 is a high performance, highly integrated radio

frequency (RF) Agile Transceiver™ designed for use in 3G and

4G base station applications. Its programmability and wideband

capability make it ideal for a broad range of transceiver applications.

The device combines a RF front end with a flexible mixed-signal

baseband section and integrated frequency synthesizers, simplifying

design-in by providing a configurable digital interface to a

processor. The AD9361 receiver LO operates from 70 MHz to

6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz

range, covering most licensed and unlicensed bands. Channel

bandwidths from less than 200 kHz to 56 MHz are supported.

The two independent direct conversion receivers have state-of-the-

art noise figure and linearity. Each receive (RX) subsystem includes

independent automatic gain control (AGC), dc offset correction,

quadrature correction, and digital filtering, thereby eliminating

the need for these functions in the digital baseband. The AD9361

also has flexible manual gain modes that can be externally

controlled. Two high dynamic range analog-to-digital converters

(ADCs) per channel digitize the received I and Q signals and pass

them through configurable decimation filters and 128-tap finite

impulse response (FIR) filters to produce a 12-bit output signal at

the appropriate sample rate.

The transmitters use a direct conversion architecture that achieves

high modulation accuracy with ultralow noise. This transmitter

design produces a best in class TX error vector magnitude (EVM)

of <−40 dB, allowing significant system margin for the external

power amplifier (PA) selection. The on-board transmit (TX)

power monitor can be used as a power detector, enabling highly

accurate TX power measurements.

The fully integrated phase-locked loops (PLLs) provide low

power fractional-N frequency synthesis for all receive and

transmit channels. Channel isolation, demanded by frequency

division duplex (FDD) systems, is integrated into the design.

All VCO and loop filter components are integrated.

The core of the AD9361 can be powered directly from a 1.3 V

regulator. The IC is controlled via a standard 4-wire serial port

and four real-time input/output control pins. Comprehensive

power-down modes are included to minimize power consumption

during normal use. The AD9361 is packaged in a 10 mm × 10 mm,

144-ball chip scale package ball grid array (CSP_BGA).

AD9361

RX1B_P,

RX1B_N

P1_[D11:D0]/

RX_[D5:D0]

P0_[D11:D0]/

TX_[D5:D0]

RADIO

SWITCHING

NOTES

1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0],

AND RADIO SWITCHING CONTAIN MULTIPLE PINS.

RX1A_P,

RX1A_N

RX1C_P,

RX1C_N

RX2B_P,

RX2B_N

RX2A_P,

RX2A_N

RX2C_P,

RX2C_N

TX_MON1

DATA INTERFACE

RX LO

TX LO

TX1A_P,

TX1A_N

TX1B_P,

TX1B_N

TX_MON2

TX2A_P,

TX2A_N

TX2B_P,

TX2B_N

CTRL

AUXDACx XTALP XTALNAUXADC

CTRL

SPI

DAC

GPO

PLLs

DAC

ADC

CLK_OUT

DAC

ADC

10453-001

AD9361 Data Sheet

Rev. F | Page 2 of 36

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Current Consumption—VDD_Interface .................................. 8

Current Consumption—VDDD1P3_DIG and VDDAx

(Combination of all 1.3 V Supplies) ......................................... 10

Absolute Maximum Ratings ..................................................... 15

Reflow Profile .............................................................................. 15

Thermal Resistance .................................................................... 15

ESD Caution ................................................................................ 15

Pin Configuration and Function Descriptions ........................... 16

Typical Performance Characteristics ........................................... 20

800 MHz Frequency Band ......................................................... 20

2.4 GHz Frequency Band .......................................................... 25

5.5 GHz Frequency Band .......................................................... 29

Theory of Operation ...................................................................... 33

General......................................................................................... 33

Receiver........................................................................................ 33

Transmitter .................................................................................. 33

Clock Input Options .................................................................. 33

Synthesizers ................................................................................. 34

Digital Data Interface................................................................. 34

Enable State Machine ................................................................. 34

SPI Interface ................................................................................ 35

Control Pins ................................................................................ 35

GPO Pins (GPO_3 to GPO_0) ................................................. 35

Auxiliary Converters .................................................................. 35

Powering the AD9361 ................................................................ 35

Packaging and Ordering Information ......................................... 36

Outline Dimensions ................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

11/2016—Rev. E to Rev. F

Changes to Features Section and General Description Section . 1

Change to Transmitter—General, Center Frequency Parameter,

Minimum Column, Table 1 ............................................................. 4

11/2014—Rev. D to Rev. E

Changes to Table 1 ............................................................................ 7

11/2013—Rev. C to Rev. D

Changes to Ordering Guide .......................................................... 36

9/2013—Revision C: Initial Version

Data Sheet AD9361

Rev. F | Page 3 of 36

SPECIFICATIONS

Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins = 1.3 V, T

= 25°C, unless otherwise noted.

Table 1.

Parameter

Symbol Min Typ Max Unit

Test Conditions/

Comments

RECEIVERS, GENERAL

Center Frequency

6000

MHz

Gain

Minimum 0 dB

Maximum 74.5 dB At 800 MHz

73.0 dB At 2300 MHz (RX1A, RX2A)

72.0 dB

At 2300 MHz (RX1B,

RX1C, RX2B, RX2C)

65.5 dB At 5500 MHz (RX1A, RX2A)

Gain Step 1 dB

Received Signal Strength

Indicator

RSSI

Range 100 dB

Accuracy ±2 dB

RECEIVERS, 800 MHz

Noise Figure NF 2 dB Maximum RX gain

Third-Order Input Intermodulation

Intercept Point

IIP3 −18 dBm Maximum RX gain

Second-Order Input

Intermodulation Intercept Point

IIP2 40 dBm Maximum RX gain

Local Oscillator (LO) Leakage −122 dBm At RX front-end input

Quadrature

Gain Error 0.2 %

Phase Error 0.2 Degrees

Modulation Accuracy (EVM) −42 dB 19.2 MHz reference clock

Input S

−10 dB

RX1 to RX2 Isolation

RX1A to RX2A, RX1C to RX2C 70 dB

RX1B to RX2B 55 dB

RX2 to RX1 Isolation

RX2A to RX1A, RX2C to RX1C 70 dB

RX2B to RX1B

RECEIVERS, 2.4 GHz

Noise Figure NF 3 dB Maximum RX gain

Third-Order Input Intermodulation

Intercept Point

IIP3 −14 dBm Maximum RX gain

Second-Order Input

Intermodulation Intercept Point

IIP2 45 dBm Maximum RX gain

LO Leakage −110 dBm

At receiver front-end

input

Quadrature

Gain Error 0.2 %

Phase Error

0.2

Degrees

Modulation Accuracy (EVM) −42 dB 40 MHz reference clock

Input S

−10 dB

RX1 to RX2 Isolation

RX1A to RX2A, RX1C to RX2C 65 dB

RX1B to RX2B 50 dB

RX2 to RX1 Isolation

RX2A to RX1A, RX2C to RX1C 65 dB

RX2B to RX1B 50 dB

AD9361 Data Sheet

Rev. F | Page 4 of 36

Parameter

Symbol Min Typ Max Unit

Test Conditions/

Comments

RECEIVERS, 5.5 GHz

Noise Figure NF 3.8 dB Maximum RX gain

Third-Order Input Intermodulation

Intercept Point

IIP3 −17 dBm Maximum RX gain

Second-Order Input

Intermodulation Intercept Point

IIP2 42 dBm Maximum RX gain

LO Leakage −95 dBm At RX front-end input

Quadrature

Gain Error 0.2 %

Phase Error 0.2 Degrees

Modulation Accuracy (EVM) −37 dB

40 MHz reference clock

(doubled internally for

RF synthesizer)

Input S

−10 dB

RX1A to RX2A Isolation 52 dB

RX2A to RX1A Isolation

TRANSMITTERS—GENERAL

Center Frequency 46.875 6000 MHz

Power Control Range 90 dB

Power Control Resolution 0.25 dB

TRANSMITTERS, 800 MHz

Output S

−10 dB

Maximum Output Power 8 dBm 1 MHz tone into 50 Ω load

Modulation Accuracy (EVM) −40 dB 19.2 MHz reference clock

Third-Order Output

Intermodulation Intercept Point

OIP3 23 dBm

Carrier Leakage −50 dBc 0 dB attenuation

−32 dBc 40 dB attenuation

Noise Floor −157 dBm/Hz 90 MHz offset

Isolation

TX1 to TX2 50 dB

TX2 to TX1 50 dB

TRANSMITTERS, 2.4 GHz

Output S

−10 dB

Maximum Output Power 7.5 dBm 1 MHz tone into 50 Ω load

Modulation Accuracy (EVM) −40 dB 40 MHz reference clock

Third-Order Output Intermod-

ulation Intercept Point

OIP3 19 dBm

Carrier Leakage −50 dBc 0 dB attenuation

−32 dBc 40 dB attenuation

Noise Floor −156 dBm/Hz 90 MHz offset

Isolation

TX1 to TX2 50 dB

TX2 to TX1 50 dB

TRANSMITTERS, 5.5 GHz

Output S

−10 dB

Maximum Output Power 6.5 dBm 7 MHz tone into 50 Ω load

Modulation Accuracy (EVM) −36 dB

40 MHz reference clock

(doubled internally for

RF synthesizer)

Third-Order Output

Intermodulation Intercept Point

OIP3 17 dBm

Carrier Leakage −50 dBc 0 dB attenuation

−30 dBc 40 dB attenuation

Noise Floor −151.5 dBm/Hz 90 MHz offset

Isolation

TX1 to TX2

TX2 to TX1 50 dB

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miaoxuerong

2022-06-08

不错，感谢分享

weixin_43597237

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