HDMI转MIPI专用ICTC358870XBG_TC358870

HDMI

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TC358870XBG

1 / 21 2017-10-25

Rev. 1.53

Toshiba Electronic Devices & Storage Corporation

CMOS Digital Integrated Circuit Silicon Monolithic

TC358870XBG

Mobile Peripheral Devices

Overview

TC358870XBG, Ultra HD to DSI, bridge converts high resolution

(higher than 4 Gbps) HDMI® stream to MIPI® DSI Tx video. It is a

follow up device of TC358779XBG, without scalar functionality. The

HDMI-RX runs at 297 MHz to carry up to 7.2 Gbps video stream. It

requires dual link MIPI DSI Tx, 1 Gbps/data lane, to transmit out a

maximum 7.2 Gbps video data.

The bridge chip is necessary for current and next generation Application Processors to drive a (dual) DSI

link display by using its HDMI Tx output port.

Features

● HDMI-RX Interface

 HDMI 1.4b

- Video Formats Support (Up to 4K×2K / 30fps),

maximum 24 bps (bit-per-pixel) no deep color

support

 RGB, YCbCr444: 24-bpp

 YCbCr422: 24-bpp

- Color Conversion

 4:2:2 to 4:4:4 is supported

 4:4:4: to 4:2:2 is supported

 RGB888 to YCbCr (4:4:4 / 4:2:2) is

supported

 YCbCr (4:4:4 / 4:2:2) to RGB888/666 is

supported

 Note: for RGB666 (R=R[5:0],2'b00,

G=G[5:0],2'b00, B=G[5:0],2'b00)

- Maximum HDMI clock speed: 297 MHz

- Audio Supports

 Internal Audio PLL to track N/CTS value

transmitted by the ACR packet.

- 3D Support

- Support HDCP1.4 decryptions (optional)

- EDID Support, Release A, Revision 1 (Feb 9,

2000)

 First 128 byte (EDID 1.3 structure)

 First E-EDID Extension: 128 bytes of CEA

Extension version 3 (specified in

CEA-861-D)

 Embedded 1K-byte SRAM (EDID_SRAM)

 Does not support Audio Return Path and HDMI

Ethernet Channels

● DSI TX Interface

 MIPI DSI compliant (Version 1.1 22 November

2011)

 Dual links DSI (DSI0 and DSI1), each link

supports 4 data lanes @1 Gbps/ data lane

- DSI0 carries the left half data of HDMI Rx

video stream and DSI1 carries the right one at

the default configuration.

- Left or right data can be

assigned/programmed to either DSI Tx link

- The maximum length of each half is limited to

2048-pixel plus up to full length overlap, DSI0

data length could be different from that of

DSI1's

- The maximum Hsync skew between DSI0

and DSI1 can be less than 10 ByteClk

 Single link DSI, maximum horizontal pixel width

- 2558 pixels (24-bit per pixel)

- 3411 pixels (16-bit per pixel)

 Supports video data formats

- RGB666, RGB888, YCbCr444, YCbCr 422

16-bit and YCbCr 422 24-bit

- YCbCr inputs can be converted into RGB

before outputting

● I

C Interface

 Support for normal (100 kHz), fast mode (400

kHz) and ultrafast mode (2 MHz)

 Slave Mode

- To be used by an external Master to configure

all TC358870XBG internal registers, including

EDID_SRAM and panel control

- Support 2 I

C Slave Addresses (0x0F &

0x1F) selected through boot-strap pin (INT)

● Audio Output Interface

 Up to four I2S data lines for supporting

multi-Channel audio data (5.1 and 7.1)

 Maximum audio sample frequency supported is

192 kHz @8 CH

 Support 16, 18, 20 or 24-bit data (depend on

HDMI input stream)

 Support Master Clock output only

 Support 32 bit-wide time-slot only

 Output Audio Over Sampling clock (256fs)

P-VFBGA80-0707-0.65-001

Weight: 67 mg (Typ.)

TC35

8870XBG

TC358870XBG

3 / 21 2017-10-25

Table of contents

REFERENCES ..................................................................................................................................................... 6

1. Overview .......................................................................................................................................................... 7

2. External Pins .................................................................................................................................................... 8

2.1. TC358870XBG 80-Pin Count Summary ................................................................................................. 10

2.2. Pin Layout ................................................................................................................................................ 10

3. Package ......................................................................................................................................................... 11

4. Electrical Characteristics ................................................................................................................................ 12

4.1. Absolute Maximum Ratings ..................................................................................................................... 12

4.2. Operating Condition................................................................................................................................. 12

4.3. DC Electrical Specification ...................................................................................................................... 13

5. External Circuit Suggestion ............................................................................................................................ 15

5.1. I

C Slave address definition .................................................................................................................... 15

5.2. HDMI ........................................................................................................................................................ 15

5.3. Audio PLL ................................................................................................................................................ 16

5.4. Suggestion of Power supply circuit ......................................................................................................... 17

6. Revision History ............................................................................................................................................. 20

RESTRICTIONS ON PRODUCT USE ............................................................................................................... 21

List of Figures

Figure 1.1 TC358870XBG System Overview ............................................................................................ 7

Figure 2.1 TC358870XBG 80-Pin Layout (Top View).............................................................................. 10

Figure 3.1 TC358870XBG package (P-VFBGA80-0707-0.65-001) ........................................................ 11

Figure 5.1 Example of DDC I/F Connection ............................................................................................ 15

Figure 5.2 Connection of REXT resistance.............................................................................................. 16

Figure 5.3 Audio Clock External LPF circuit block diagram ..................................................................... 16

Figure 5.4 Suggestion of power supply circuit with external switch ........................................................ 17

Figure 5.5 Suggestion of power supply circuit with current protection regulator ..................................... 18

Figure 5.6 Suggestion of power supply circuit at VDDIO18 = 3.3V ......................................................... 19

List of Tables

Table 2.1 TC358870XBG Functional Signal List ....................................................................................... 8

Table 2.2 BGA80 Pin Count Summary .................................................................................................... 10

Table 3.1 Mechanical Dimension ............................................................................................................. 11

Table 6.1 Revision History ....................................................................................................................... 20

TC358870XBG

5 / 21 2017-10-25

1 NOTICE OF DISCLAIMER

2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled

3 by any of the authors or developers of this material or MIPI. The material contained herein is provided on

4 an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS

5 AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all

6 other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if

7 any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of

8 accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of

9 negligence.

10 All materials contained herein are protected by copyright laws, and may not be reproduced, republished,

11 distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express

12 prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related

13 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and

14 cannot be used without its express prior written permission.

15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET

16 POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD

17 TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY

18 AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR

19 MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE

20 GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,

21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER

22 CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR

23 ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,

24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH

25 DAMAGES.

26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is

27 further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the

28 contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;

29 and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance

30 with the contents of this Document. The use or implementation of the contents of this Document may

31 involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,

32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI

33 does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any

34 IPR or claims of IPR as respects the contents of this Document or otherwise.

35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:

36 MIPI Alliance, Inc.

37 c/o IEEE-ISTO

38 445 Hoes Lane

39 Piscataway, NJ 08854

40 Attn: Board Secretary

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