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____________________________________________________________________________________________________________________
CONFIDENTIAL
1
© 2017 Kingston Solutions Inc.
Flash Storage Specification e•MMC™ 5.0
Flash Storage Specification
e•MMC™ 4.5
Flash Storage Specification
e•MMC™ 4.5
Embedded Multimedia Card
(e•MMC
™
5.0 HS400)
04EPOP04-NL3DM627
04EPOP08-NL3DM627
Datasheet
V1.0
Kingston Solutions Inc.

____________________________________________________________________________________________________________________
CONFIDENTIAL
2
© 2017 Kingston Solutions Inc.
Flash Storage Specification e•MMC™ 5.0
Flash Storage Specification
e•MMC™ 4.5
Flash Storage Specification
e•MMC™ 4.5
CONTENTS
Product Features: ..................................................................................................................................................5
1. Introduction ........................................................................................................................................................7
1.1. e•MMC
™
Standard Specification ................................................................................................................7
1.2. LPDDR3 Standard Specification ...............................................................................................................7
1.3. Device Block Diagram ..................................................................................................................................7
2. Specification .......................................................................................................................................................8
2.1. System Performance ....................................................................................................................................8
2.2. Power Consumption .....................................................................................................................................8
2.3. Capacity according to partition ................................................................................................................8
2.4. User Density ....................................................................................................................................................8
3. e•MMC
™
Device and System ...........................................................................................................................9
3.1. e•MMC
™
System Overview ..........................................................................................................................9
3.2. Memory Addressing .....................................................................................................................................9
3.3. e•MMC
™
Device Overview ........................................................................................................................ 10
3.3.1 Clock (CLK) ........................................................................................................................................... 10
3.3.2 Data Strobe(DS).................................................................................................................................. 10
3.3.3 Command (CMD) ................................................................................................................................ 10
3.3.4 Input/Outputs (DAT0-DAT7) ........................................................................................................ 10
3.4. Bus Protocol ................................................................................................................................................. 11
3.5. Bus Speed Modes ........................................................................................................................................ 11
3.5.1 HS200 Bus Speed Mode ................................................................................................................... 12
3.5.2 HS200 System Block Diagram ....................................................................................................... 12
3.5.3 HS400 Bus Speed mode ................................................................................................................... 12
3.5.4 HS400 System Block Diagram ....................................................................................................... 13
4. e•MMC
™
Functional Description ............................................................................................................... 14
4.1 e•MMC
™
Overview....................................................................................................................................... 14
4.2 Boot Operation Mode ................................................................................................................................ 14
4.3 Device Identification Mode ..................................................................................................................... 14
4.4 Interrupt Mode ............................................................................................................................................ 14
4.5 Data Transfer Mode ................................................................................................................................... 14
4.6 Inactive Mode .............................................................................................................................................. 15
4.7 H/W Reset Operation ................................................................................................................................ 15
4.8 Noise Filtering Timing for H/W Reset ................................................................................................. 16
4.9 Field Firmware Update(FFU) ................................................................................................................. 17
4.10 Power off Notification for sleep .......................................................................................................... 18
5. Register Settings ............................................................................................................................................ 20
5.1. OCR Register ................................................................................................................................................ 20
5.2. CID Register .................................................................................................................................................. 20
5.3. CSD Register ................................................................................................................................................. 20
5.4. Extended CSD Register ............................................................................................................................. 20

____________________________________________________________________________________________________________________
CONFIDENTIAL
3
© 2017 Kingston Solutions Inc.
Flash Storage Specification e•MMC™ 5.0
Flash Storage Specification
e•MMC™ 4.5
Flash Storage Specification
e•MMC™ 4.5
5.5. RCA Register ................................................................................................................................................. 20
5.6. DSR Register ................................................................................................................................................. 20
6. The e•MMC
™
bus ............................................................................................................................................. 21
6.1 Power-up ....................................................................................................................................................... 22
6.1.1 e•MMC
™
power-up ............................................................................................................................. 22
6.1.2 e•MMC
™
Power Cycling ..................................................................................................................... 23
6.2 Bus Operating Conditions ....................................................................................................................... 24
6.2.1 Power supply: e•MMC
™
.................................................................................................................... 24
6.2.2 e•MMC
™
Power Supply Voltage ..................................................................................................... 25
6.2.3 Bus Signal Line Load ......................................................................................................................... 26
6.2.4 HS400 reference load ....................................................................................................................... 27
6.3 Bus Signal Levels ........................................................................................................................................ 28
6.4.1 Open-drain Mode Bus Signal Level .............................................................................................. 28
6.4.2 Push-pull mode bus signal level— e•MMC
™
.............................................................................. 28
6.4.3 Bus Operating Conditions for HS200 & HS400 ........................................................................ 29
6.4.4 Device Output Driver Requirements for HS200 & HS400 ................................................... 29
6.5 Bus Timing .................................................................................................................................................... 29
6.5.1 Device Interface Timings ................................................................................................................ 30
6.6 Bus Timing for DAT Signals During Dual Data Rate Operation.................................................. 31
6.7 Bus Timing Specification in HS200 Mode .......................................................................................... 33
6.8 Bus Timing Specification in HS400 mode .......................................................................................... 37
6.8.1 HS400 Device Input Timing ........................................................................................................... 37
6.8.2 HS400 Device Output Timing ........................................................................................................ 38
7. LPDDR3 Interface .......................................................................................................................................... 40
7.1 Pin Function and Descriptions .............................................................................................................. 40
7.2 Simplified State Diagram ......................................................................................................................... 41
7.3 Electrical Conditions ................................................................................................................................. 42
7.3.1 Absolute Maximum Ratings ........................................................................................................... 42
7.3.2 Recommended DC Operating Conditions .................................................................................. 42
7.1.1 AC and DC Input Measurement Levels ....................................................................................... 43
7.1.2 VREF Tolerances ................................................................................................................................ 44
7.1.3 Input Signal .......................................................................................................................................... 45
7.1.4 Differential Input Cross Point Voltage ....................................................................................... 48
7.1.5 Slew Rate Definitions for Single-Ended Input Signals .......................................................... 49
7.1.6 Slew Rate Definitions for Differential Input Signals ............................................................. 49
7.1.7 AC and DC Output Measurement Levels .................................................................................... 50
7.1.8 Differential Output Slew Rate ....................................................................................................... 52
7.1.9 Overshoot and Undershoot Specifications ............................................................................... 53
7.1.10 RONPU and RONPD Resistor Definition .................................................................................. 54
7.2 Electrical Specifications ........................................................................................................................... 59
7.2.1 IDD Measurement Conditions ....................................................................................................... 59
7.2.2 IDD Specifications ............................................................................................................................. 62
7.2.3 IDD Specifications (cont’d) ............................................................................................................. 64
7.2.4 DC Characteristics 1 .......................................................................................................................... 65

____________________________________________________________________________________________________________________
CONFIDENTIAL
4
© 2017 Kingston Solutions Inc.
Flash Storage Specification e•MMC™ 5.0
Flash Storage Specification
e•MMC™ 4.5
Flash Storage Specification
e•MMC™ 4.5
7.2.5 DC Characteristics 2 .......................................................................................................................... 67
7.2.6 Pin Capacitance (For 4Gb) .............................................................................................................. 68
7.2.7 Clock Specification ............................................................................................................................ 68
7.2.8 Period Clock Jitter ............................................................................................................................. 70
7.2.9 LPDDR3 Refresh Requirements by Device Density ............................................................... 74
7.2.10 AC Characteristics ........................................................................................................................... 75
7.2.11 CA and CS_n Setup, Hold and Derating .................................................................................... 82
7.2.12 Power Ramp and Device Initialization .................................................................................... 84
7.2.13 Initialization After Reset (without Power Ramp): .............................................................. 87
7.2.14 Power-Off Sequence ....................................................................................................................... 87
7.2.15 Uncontrolled Power-Off Sequence ............................................................................................ 88
7.2.16 Command truth table. ................................................................................................................... 89
7.2.17 CKE Truth Table .............................................................................................................................. 91
7.3 Mode Register Definition ......................................................................................................................... 92
8. Package connections ................................................................................................................................. 102
9. Ball Assignment (136 ball) ...................................................................................................................... 104
10. Temperature ................................................................................................................................................ 105
11. Marking .......................................................................................................................................................... 105
12. Revision History .......................................................................................................................................... 106

____________________________________________________________________________________________________________________
CONFIDENTIAL
5
© 2017 Kingston Solutions Inc.
Flash Storage Specification e•MMC™ 5.0
Flash Storage Specification
e•MMC™ 4.5
Flash Storage Specification
e•MMC™ 4.5
Product Features:
<Common>
• Package : 136 ball FBGA Type –10.0mm x 10.0mm x (Max 0.9mm) for 04EPOP04-NL3DM627
• Package : 136 ball FBGA Type –10.0mm x 10.0mm x (Max 1.0mm) for 04EPOP08-NL3DM627
• Separate e•MMC™ and LPDRAM interfaces
• Lead-free (RoHS compliant) and Halogen-free
• Operating temperature range: –25°C to +85°C
< e•MMC
™
- NAND>
• Packaged NAND flash memory with e•MMC™ 5.0 interface
• Compliant with e•MMC™ Specification Ver.4.4, 4.41,4.5,5.0
• Bus mode
- High-speed e•MMC
™
protocol
- Clock frequency : 0-200MHz.
- Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
• Supports three different data bus widths : 1 bit(default), 4 bits, 8 bits
- Data transfer rate: up to 52Mbyte/s (using 8 parallel data lines at 52 MHz)
- Single data rate : up to 200Mbyte/s @ 200MHz
- Dual data rate : up to 400Mbytes/s@200MHz
• Supports (Alternate) Boot Operation Mode to provide a simple boot sequence method
• Supports SLEEP/AWAKE (CMD5).
• Host initiated explicit sleep mode for power saving
• Enhanced Write Protection with Permanent and Partial protection options
• Supports Multiple User Data Partition with Enhanced User Data Area options
• Supports Background Operations & High Priority Interrupt (HPI)
• Supports enhanced storage media feature for better reliability
• Operating voltage range :
- VCCQ = 1.8 V/3.3 V
- VCC = 3.3 V
• Error free memory access
- Internal error correction code (ECC) to protect data communication
- Internal enhanced data management algorithm
- Solid protection of sudden power failure safe-update operations for data content
• Security
- Support secure bad block erase commands
- Enhanced write Protection with permanent and partial protection options
• Quality
- RoHS compliant (for detailed RoHS declaration, please contact your KSI representative.)
• Supports Field Firmware Update(FFU)
• Enhanced Device Life time
• Supports Pre EOL information
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