KEA128Sub-FamilyReferenceManual_S9KEA

5星 · 超过95%的资源需积分: 10 199 浏览量更新于2023-05-30 评论收藏 7.54MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

KEA128 Sub-Family Reference

Manual

Supports:S9KEAZ64AMLK(R), S9KEAZ128AMLK(R),

S9KEAZ64AVLK(R), S9KEAZ128AVLK(R), S9KEAZ64ACLK(R),

S9KEAZ128ACLK(R), S9KEAZ64AMLH(R), S9KEAZ128AMLH(R),

S9KEAZ64AVLH(R), S9KEAZ128AVLH(R), S9KEAZ64ACLH(R) and

S9KEAZ128ACLH(R)

Document Number: S9KEA128Z80M48SF0RM

Rev 2, July 2014

Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.........................................................................................................................................................................37

1.1.1 Purpose.............................................................................................................................................................37

1.1.2 Audience.......................................................................................................................................................... 37

1.2 Conventions.................................................................................................................................................................... 37

1.2.1 Numbering systems..........................................................................................................................................37

1.2.2 Typographic notation....................................................................................................................................... 38

1.2.3 Special terms....................................................................................................................................................38

Chapter 2

Introduction

2.1 Overview.........................................................................................................................................................................39

2.2 Module functional categories..........................................................................................................................................39

2.2.1 ARM Cortex-M0+ core modules..................................................................................................................... 40

2.2.2 System modules............................................................................................................................................... 41

2.2.3 Memories and memory interfaces....................................................................................................................42

2.2.4 Clocks...............................................................................................................................................................42

2.2.5 Security and integrity modules........................................................................................................................ 42

2.2.6 Analog modules............................................................................................................................................... 43

2.2.7 Timer modules................................................................................................................................................. 43

2.2.8 Communication interfaces............................................................................................................................... 44

2.2.9 Human-machine interfaces.............................................................................................................................. 44

2.2.10 Orderable part numbers....................................................................................................................................45

Chapter 3

Chip Configuration

3.1 Introduction.....................................................................................................................................................................47

3.2 Module to Module Interconnects....................................................................................................................................47

3.2.1 Interconnection overview.................................................................................................................................47

KEA128 Sub-Family Reference Manual, Rev. 2, July 2014

Freescale Semiconductor, Inc. 3

Section number Title Page

3.2.2 Analog reference options................................................................................................................................. 51

3.2.3 ACMP output capture...................................................................................................................................... 51

3.2.4 UART0_TX modulation.................................................................................................................................. 52

3.2.5 UART0/1/2_RX capture.................................................................................................................................. 52

3.2.6 UART0_RX filter............................................................................................................................................ 53

3.2.7 RTC capture..................................................................................................................................................... 54

3.2.8 FTM2 software synchronization...................................................................................................................... 54

3.2.9 ADC hardware trigger......................................................................................................................................54

3.3 Core Modules..................................................................................................................................................................55

3.3.1 ARM Cortex-M0+ core configuration............................................................................................................. 55

3.3.1.1 ARM Cortex M0+ core ...............................................................................................................55

3.3.1.2 Buses, interconnects, and interfaces............................................................................................ 56

3.3.1.3 System Tick Timer.......................................................................................................................56

3.3.1.4 Core privilege levels.................................................................................................................... 57

3.3.1.5 Caches.......................................................................................................................................... 57

3.3.2 Nested Vectored Interrupt Controller (NVIC) configuration...........................................................................57

3.3.2.1 Interrupt priority levels................................................................................................................ 58

3.3.2.2 Non-maskable interrupt................................................................................................................58

3.3.2.3 Interrupt channel assignments......................................................................................................58

3.3.3 Asynchronous wakeup interrupt controller (AWIC) configuration.................................................................61

3.3.3.1 Wakeup sources........................................................................................................................... 61

3.4 System Modules..............................................................................................................................................................62

3.4.1 SIM configuration............................................................................................................................................62

3.4.2 PMC configuration...........................................................................................................................................63

3.4.3 MCM configuration......................................................................................................................................... 63

3.4.4 Crossbar-light switch configuration.................................................................................................................64

3.4.4.1 Crossbar-Light switch master assignments..................................................................................65

3.4.4.2 Crossbar switch slave assignments.............................................................................................. 65

KEA128 Sub-Family Reference Manual, Rev. 2, July 2014

4 Freescale Semiconductor, Inc.

Section number Title Page

3.4.5 Peripheral bridge configuration....................................................................................................................... 65

3.4.5.1 Number of peripheral bridges...................................................................................................... 66

3.4.5.2 Memory maps.............................................................................................................................. 66

3.5 System Security.............................................................................................................................................................. 66

3.5.1 CRC configuration........................................................................................................................................... 66

3.5.2 Watchdog configuration...................................................................................................................................67

3.5.2.1 WDOG clocks..............................................................................................................................68

3.5.2.2 WDOG operation......................................................................................................................... 68

3.6 Clock Modules................................................................................................................................................................69

3.6.1 ICS configuration.............................................................................................................................................69

3.6.1.1 Clock gating................................................................................................................................. 69

3.6.2 OSC configuration........................................................................................................................................... 70

3.7 Memories and Memory Interfaces..................................................................................................................................70

3.7.1 Flash memory configuration............................................................................................................................ 70

3.7.1.1 Flash memory sizes......................................................................................................................71

3.7.1.2 Flash memory map.......................................................................................................................71

3.7.1.3 Alternate Non-Volatile IRC User Trim Description....................................................................72

3.7.1.4 Flash security............................................................................................................................... 72

3.7.1.5 Erase all flash contents.................................................................................................................72

3.7.2 Flash memory controller configuration............................................................................................................73

3.7.3 SRAM configuration........................................................................................................................................73

3.7.3.1 SRAM sizes..................................................................................................................................74

3.7.3.2 SRAM ranges...............................................................................................................................74

3.7.3.3 SRAM bit operation.....................................................................................................................76

3.8 Analog.............................................................................................................................................................................76

3.8.1 12-bit analog-to-digital converter (ADC) configuration..................................................................................76

3.8.1.1 ADC instantiation information.....................................................................................................77

3.8.1.2 ADC0 connections/channel assignment.......................................................................................77

3.8.1.3 ADC analog supply and reference connections........................................................................... 78

KEA128 Sub-Family Reference Manual, Rev. 2, July 2014

Freescale Semiconductor, Inc. 5