CSR8675_datasheet

csr8675

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BlueCore

󰀲

Bluetooth

v4.1 specification fully qualified

󰀲

Radio includes integrated balun

󰀲

80 MHz RISC MC≥ and 120 MHz Kalimba DSP

󰀲

≥p to 120 MIPS DSP for intensive digital signal

processing algorithms

󰀲

24-bit audio

󰀲

16 Mb internal flash; optional support for 64 Mb of

external SPI flash

󰀲

Stereo codec with 2 channels of ADC and up to 6

microphone inputs (includes bias generation and

digital microphone support)

󰀲

Audio interfaces:

󰀲

2 x I²S/PCM

󰀲

1 x SPDIF (independent of I²S/PCM ports)

󰀲

Serial interfaces: ≥AR≤, ≥SB 2.0 full-speed, I²C

and SPI

󰀲

Integrated dual switch-mode regulators, linear

regulators and battery charger

󰀲

3 hardware LED controllers (for RGB) and ability to

drive LCD segment display directly

󰀲

Support for up to 6 capacitive touch sensor inputs

󰀲

4.84 x 4.84 x 0.6mm, 0.5mm pitch 79-ball WLCSP

󰀲

CSR8675 WLCSP application boards backward

compatible with CSR8670 WLCSP

󰀲

Green (RoHS compliant and no antimony or

halogenated flame retardants)

Low-power Solution

for

CSR8675 WLCSP consumer audio platform for wired

and wireless applications integrates an ultralowpower

DSP and application processor with embedded flash

memory, a high-performance stereo codec, a power

management subsystem, LED and LCD drivers and

capacitive touch sensor inputs in a SoC IC.

2.4 GHz

Radio

Balun

I/O

B≤_RF RAM

Baseband

MC≥

Kalimba

DSP

Flash

X≤AL

Serial Flash

Exter nal

Memory

≥AR≤/≥SB

PIO

Audio In / Out

PCM/I

SPI /I

LED /PIO

Audio

Interface

Capacitive

Sense

Clock

Gener ati on

SPDIF

PCM/I

󰀲

High-end wired/wireless stereo headphones

󰀲

High-end wired/wireless stereo headsets

󰀲

High-end wired/wireless active headsets

󰀲

Wireless stereo speakers

󰀲

Low-end docking stations and soundbars

󰀲

Gaming headsets

≤he dual-core architecture with flash memory enables

manufacturers to easily differentiate their products with

new features without extending development cycles.

≤he enhanced Kalimba DSP coprocessor with up to

120 MIPS supports more digital signal processing

requirements in stereo headphones, headsets, gaming

headsets and soundbars.

≤he audio codec supports 2 ADC channels, up to 6

microphone inputs, stereo output and a variety of audio

standards.

CSR's popular BlueCore

CSR8670



and

BlueCore

5Multimedia platforms are

softwareportable to the CSR8675 WLCSP, with easy

migration of a broad range of solutions from CSR's

eXtension partners. ≤his enables rapid time-to-market

deployment for a broad range of consumer electronic

products.

Production Information

Confidential Information - ≤his Material is Subject to CSR's Non-Disclosure Agreement

Page 1 of 110

CS-232427-DSP4

www.csr.com

CSR8675 WLCSP

Data Sheet

Prepared for customer=Wheeler Hu - goertek.com - 23-Aug-2017

󰀲 Dualmode Bluetooth low energy radio

󰀲 Support for Bluetooth basic rate / EDR and low energy

connections

󰀲 3 Bluetooth low energy connections at the same time as

basic rate A2DP

󰀲 Onchip balun (50  impedance in ≤X and RX modes)

󰀲 No external trimming is required in production

󰀲 Bluetooth v4.1 specification software/hardware

󰀲 ≤ypical RF transmit power

󰀲 Basic rate 8.5 dBm

󰀲 EDR -1 dB (relative power)

󰀲 Bluetooth low energy 8 dBm

󰀲 6bit DAC level control

󰀲 Class 1, Class 2 and Class 3 support without the need for

an external power amplifier or ≤X/RX switch

󰀲 ≤ypical RF receiver sensitivity:

󰀲 Basic rate -91.0 dBm

󰀲 EDR -92.5 dBm

󰀲 Bluetooth low energy -93.0 dBm

󰀲 Integrated channel filters

󰀲 Digital demodulator for improved sensitivity and cochannel

rejection

󰀲 Realtime digitised RSSI available to application

󰀲 Fast AGC for enhanced dynamic range

󰀲 Channel classification for AFH

󰀲 Fully integrated synthesiser requires no external VCO,

varactor diode, resonator or loop filter

󰀲 Compatible with crystals 19.2 MHz to 32 MHz or an external

clock 19.2 MHz to 40 MHz (default 26 MHz)

󰀲 Enhanced Kalimba 5 DSP coprocessor

󰀲 120 MHz clock, up to 120 MIPS performance

󰀲 24bit fixed-point core

󰀲 Singlecycle MAC:

󰀲 24 x 24bit multiply

󰀲 56bit accumulate

󰀲 Improved architecture and instructions for better

performance over CSR8670 WLCSP

󰀲 32bit instruction word

󰀲 Dual 24bit data memory

󰀲 12 K x 32bit program RAM including 1 K instruction cache

for executing out of internal flash

󰀲 2bank data RAM:

󰀲 DM1 32 K x 24bit

󰀲 DM2 32 K x 24bit

󰀲 16 Mb internal flash

󰀲 Memory protection unit supporting accelerated VM

󰀲 56 KB internal RAM, enables fullspeed data transfer, mixed

voice/data and full piconet support

󰀲 Logic for forward error correction, header error control,

access code correlation, CRC, demodulation, encryption bit

stream generation, whitening and transmit pulse shaping

󰀲 ≤ranscoders for Alaw, µlaw and linear voice via PCM and

Alaw, µlaw and CVSD voice over air

󰀲 Audio codec with 2 highquality dedicated ADCs

󰀲 24-bit audio processing support

󰀲 1 microphone bias generator and up to 2 analogue

microphone inputs

󰀲 ≥p to 6 digital microphone inputs (MEMS)

󰀲 G.722 compatible, includes improved digital IIR filter path

for stopband attenuation required for G.722 compliance

󰀲 Enhanced sidetone gain control

󰀲 Supported sample rates of 8, 11.025, 16, 22.05, 32, 44.1,

48, 96 kHz and 192kHz (DAC only)

󰀲 ≥AR≤ interface

󰀲 ≥SB 2.0 interface (fullspeed)

󰀲 ≥p to 24 PIOs (includes 8 general purpose PIOs and unused

digital interfaces also available as PIOs)

󰀲 SPI debug and programming interface with read access

disable locking

󰀲 2 x PCM/I²S and 1 x SPDIF supported simultaneously

󰀲 Dual/quad external serial flash memory interface

󰀲 3 LED drivers (includes RGB) with PWM flasher on sleep

clock

󰀲 Support for up to 6 capacitive touch sensor inputs

󰀲 1 analogue PIOs

󰀲 2 highefficiency switchmode regulators with 1.8 V and

1.35 V outputs from battery supply

󰀲 3.3 V ≥SB pad supply linear regulator

󰀲 Lowvoltage linear regulator for internal digital supply

󰀲 Lowvoltage linear regulator for internal analogue supply

with 1.35 V output

󰀲 Poweronreset detects low supply voltage

󰀲 Power management includes digital shutdown and wakeup

commands with lowpower crystal drive for ultralow power

Park/Sniff/Hold mode

󰀲 Lithium ion / Lithium polymer battery charger with instanton

󰀲 Fast charging support up to 200 mA with no external

components

󰀲 Higher charge currents using external pass device

󰀲 Supports ≥SB BCv1.2 CDP, DCP and SDP charger

detection

󰀲 Charger precalibrated by CSR

󰀲 PSE compliance:

󰀲 Design to JISC 8712/8714 (batteries)

󰀲 ≤esting based on IEEE 1725

󰀲 Customer application space available

󰀲 Crystal oscillator with builtin digital trimming

󰀲 Auxiliary ADC and DAC available to applications

󰀲 4.84 x 4.84 x 0.6mm, 0.5mm pitch 79-ball WLCSP

Production Information

Confidential Information - ≤his Material is Subject to CSR's Non-Disclosure Agreement

Page 3 of 110

CS-232427-DSP4

www.csr.com

CSR8675 WLCSP

Data Sheet

Prepared for customer=Wheeler Hu - goertek.com - 23-Aug-2017

剩余109页未读，继续阅读

chairys

2017-09-10

不错，这个资料很多地方找不到

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