PCIEL1SS-L1PMSubstateswithCLKREQ1.0a_pciel1substae如何进入

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Page 1

PCI-SIG ENGINEERING CHANGE NOTICE

TITLE:

L1 PM Substates with CLKREQ, Revision 1.0a

DATE:

Last Modified 15 Aug 2012 31 May 2013;

Protocol Workgroup Final Approval: 23 Aug 2012

Errata for Rev 1.0a PWG approved 30 May 2013

AFFECTED

DOCUMENTS:

PCI Express Base Specification Revision 3.0,

PCI Express Base Specification Revision 2.1,

PCI Express Mini Card Electromechanical Specification Revision

1.2,

PCI Express Card Electromechanical Specification Revision 2.0,

8.0 GT/s Receiver Impedance ECN

SPONSOR:

Intel Corporation, Hewlett-Packard Company

Part I

1. Summary of the Functional Changes

This ECR defines an optional mechanism, that establishes, depending on implementation, one or

more substates of the L1 Link state, which allow for dramatically lower idle power, including near

complete removal of power for high speed circuits. The new L1 PM Substates are applicable in

both the ASPM and PCI-PM L1 Link states. L1 PM Substate management utilizes a per-Link

sideband signal called CLKREQ#. For those implementations that already have a CLKREQ#

signal, the CLKREQ# signal is repurposed and results in no new pins being required. For other

implementations, the CLKREQ# signal needs to be added; the number of pins and associated

routing linearly scales with the number of Ports.

As noted above, this ECN defines functionality based on the use of CLKREQ#. A subsequent ECN

is planned to define an in-band mechanism that would provide similar capabilities to those defined

in this ECN using CLKREQ#.

2. Benefits as a Result of the Changes

Current PCIe specifications do not provide mechanisms to enable very lower power consumption

when a PCIe Link is idle. This limits the application of PCIe technologies in low-power and

battery-based applications such as embedded, handheld and tablet computers. It also leads to

excessive power waste in high-lane-count PCIe solutions such as desktops, servers, storage, and

PCIe Switch-based solutions. Further, with the growing world-wide attention to power efficiency,

economic as well as increased regulatory requirements are driving the need to enhance the PCIe

specifications to reduce idle power consumption.

3. Assessment of the Impact

The new mechanism impacts all components that support this optional capability. The new

mechanism is only enabled when supported by both Ports on a Link and the Link itself (due to the

required sideband signal). If any component does not support the capability, then the capability

must not be enabled and the solution continues to operate using the existing legacy L1 semantics.

4. Analysis of the Hardware Implications

This ECR applies to the Link power control and reference clock mechanisms associated with a

Link between an Upstream Port and a Downstream Port. See (1) above.

PHY power gating mechanisms must be added to take advantage of the PHY power savings

opportunities enabled by this optional capability.

Page 4

Note: the following text can be found in the ECN – 8G_Receiver_Impedance

 Next state is Recovery after a 100 ms timeout if the current data rate is 8.0 GT/s or

higher and the Port’s Receivers do not meet the ZRX-DC specification for 2.5 GT/s (see

Table 4-24). All Ports are permitted, but not encouraged, to implement the timeout and

transition to Recovery when the data rate is 8.0 GT/s or higher.

o This timeout is not affected by the L1 PM Substates mechanism.

…

5.2. Link State Power Management

PCI Express defines Link power management states, replacing the bus power management

states that were defined by the PCI Bus Power Management Interface Specification. …

…

L1 – Higher latency, lower power “standby” state.

L1 support is required for PCI-PM compatible power management. L1 is optional for

ASPM unless specifically required by a particular form factor.

When L1 PM Substates is enabled by setting one or more of the enable bits in the L1 PM

Substates Control 1 Register this state is referred to as the L1.0 substate.

All main power supplies must remain active during L1. As long as they adhere to the

advertised L1 exit latencies, implementations are explicitly permitted to reduce power by

applying techniques such as, but not limited to, periodic rather than continuous checking

for Electrical Idle exit, checking for Electrical Idle exit on only one Lane, and powering

off of unneeded circuits. All platform-provided component reference clocks must remain

active during L1, except as permitted by Clock Power Management and/or L1 PM

Substates when enabled. A component’s internal PLLs may be shut off during L1,

enabling greater power savings at a cost of increased exit latency.

The L1 state is entered whenever all Functions of a Downstream component on a given

Link are programmed to a D-state other than D0. The L1 state also is entered if the

Downstream component requests L1 entry (ASPM) and receives positive

acknowledgement for the request.

Exit from L1 is initiated by an Upstream-initiated transaction targeting a Downstream

component, or by the Downstream component’s initiation of a transaction heading

Upstream. Transition from L1 to L0 is typically a few microseconds.

TLP and DLLP transmission is disabled for a Link in L1.

L1 PM Substates – optional L1.1 and L1.2 substates of the L1 low power Link state for PCI-

PM and ASPM.

In the L1.1 substate, the Link common mode voltages are maintained. The L1.1 substate is

entered when the Link is in the L1.0 substate and conditions for entry into L1.1 substate are

met. See Section 5.5.1. for details.

For example, disabling the internal PLL may be something that is desirable when in D3

hot

, but not

so when in D1 or D2.

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