library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity frequence is
port ( bclk : in std_logic;
tclk : in std_logic;
clr : in std_logic;
gate : in std_logic;
-- rd : in std_logic;
adr : in std_logic_vector(2 downto 0);
data : out std_logic_vector(7 downto 0) );
end frequence;
architecture behav of frequence is
signal bzq,tsq : std_logic_vector(31 downto 0);
signal ena : std_logic;
begin
data <= bzq(7 downto 0 ) when adr = "000" else
bzq(15 downto 8 ) when adr = "001" else
bzq(23 downto 16) when adr = "010" else
--bzq(31 downto 24) when adr = "011" else
--read bzq
tsq(7 downto 0 ) when adr = "100" else
tsq(15 downto 8 ) when adr = "101" else
tsq(23 downto 16) when adr = "110" else
"00000000";--else--
--tsq(31 downto 24) ;
--read tsq
bzpr:process(bclk,clr)--board signal
begin
if clr = '1' then bzq <= (others => '0');
elsif bclk'event and bclk = '1' then
if ena = '1' then bzq <= bzq+1;
end if;
end if;
end process;
tspr:process(tclk,clr)--test signal
begin
if clr = '1' then tsq <= (others => '0');
elsif tclk'event and tclk = '1' then
if ena = '1' then tsq <= tsq+1;
end if;
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