KMR8X0001M-B608规格书

EMMC

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KMR8X0001M-B608

Rev. 0.0, Sep. 2013

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

Preliminary

MCP Specification

16GB e.MMC

+ 16Gb QDP LPDDR3 SDRAM

datasheet

EMMC

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KMR8X0001M- B608 MCP Memory

Preliminary Rev. 0.0

datasheet

1. FEATURES

embedded MultiMediaCard Ver. 5.0 compatible. Detail description is refer-

enced by JEDEC Standard

SAMSUNG e·MMC supports features of eMMC5.0 which are defined in

JEDEC Standard

- Supported Features : Packed command, Cache, Discard, Sanitize,

Power Off Notification, Data Tag, Partition types, Context ID, Real Time

Clock, Dynamic Device Capacity, HS200

- Non-supported Features : Large Sector Size (4KB)

 Additional features of eMMC5.0 : HS400 mode (200MHz DDR - up to

400Mbps), Field Firmware Update, Device Health Report, Sleep Notifica-

tion, Secure Removal Type

 Full backward compatibility with previous MultiMediaCard system specifi-

cation (1bit data bus, multi-e·MMC systems)

 Data bus width : 1bit (Default), 4bit and 8bit

 MMC I/F Clock Frequency : 0 ~ 200MHz

MMC I/F Boot Frequency : 0 ~ 52MHz

 Power : Interface power → VDD(VCCQ) (1.70V ~ 1.95V or 2.7V ~ 3.6V) ,

Memory power → VDDF(VCC) (2.7V ~ 3.6V)

Operating Temperature : -25C ~ 85C

Package : 221Ball FBGA Type - 11.5mm x 13mm x 1.2mmt

0.5mm ball pitch

<e.MMC>

• Double-data rate architecture; two data transfers per clock cycle

• Bidirectional data strobes (DQS_t, DQS_c), These are transmitted/

received with data to be used in capturing data at the receiver

• Differential clock inputs (CK_t and CK_c)

• Differential data strobes (DQS_t and DQS_c)

• Commands & addresses entered on both positive and negative CK

edges; data and data mask referenced to both edges of DQS

• 8 internal banks for concurrent operation

• Data mask (DM) for write data

• Burst Length: 8

• Burst Type: Sequential

• Read & Write latency : Refer to Table 45 LPDDR3 AC Timing Table

• Auto Precharge option for each burst access

• Configurable Drive Strength

• All Bank Refresh, Per Bank Refresh and Self Refresh

• Partial Array Self Refresh and Temperature Compensated Self

Refresh

• Write Leveling

• CA Calibration

• HSUL_12 compatible inputs

• VDD1/VDD2/VDDQ/VDDCA

: 1.8V/1.2V/1.2V / 1.2V

• No DLL : CK to DQS is not synchronized

• Edge aligned data output, center aligned data input

• Operating Temperature : -25 ~ 85C

• On Die Termination using ODT pin

• 2/CS, 2CKE

• In case ODT Function is not used, ODT pin should be considerd as

DNU. ODT will be connected to rank 0. The ODT Input to rank 1(if 2nd

rank is present) will be connected to Ground in the package.

NOTE :

1) The least-significant column address C0 is not transmitted on the CA bus, and is

implied to be zero.

2) t

REFI

values for all bank refresh is Tc = -25~85C, Tc means Operating Case Tem-

perature

3) Row and Column Address values on the CA bus that are not used are “don’t care.”

4) No memory present at addresses with R13=R14=HIGH. ACT command with

R13=R14=HIGH is ignored (NOP). Write to R13=R14=HIGH is ignored (NOP).

Items 4Gb

Number of Banks 8

Bank Addresses BA0-BA2

REFI

(us)

3.9

x16

Row Addresses R0-R13

Column Addresses

C0-C10

x32

Row Addresses R0-R13

Column Addresses

C0-C9

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KMR8X0001M- B608 MCP Memory

Preliminary Rev. 0.0

datasheet

2. GENERAL DESCRIPTION

The KMR8X0001M is a Multi Chip Package Memory which combines 16GB e.MMC and 16Gb QDP LPDDR3 SDRAM.

SAMSUNG e·MMC is an embedded MMC solution designed in a BGA package form. e·MMC operation is identical to a MMC device and therefore is a

simple read and write to memory using MMC protocol v5.0 which is a industry standard.

e·MMC consists of NAND flash and a MMC controller. 3V supply voltage is required for the NAND area (VDDF or VCC) whereas 1.8V or 3V dual supply

voltage (VDD or VCCQ) is supported for the MMC controller. SAMSUNG e.MMC supports 200MHz DDR – up to 400MBps with bus widths of 8 bit in order

to improve sequential bandwidth, especially sequential read performance.

There are several advantages of using e·MMC. It is easy to use as the MMC interface allows easy integration with any microprocessor with MMC host.

Any revision or amendment of NAND is invisible to the host as the embedded MMC controller insulates NAND technology from the host. This leads to

faster product development as well as faster times to market.

The embedded flash management software or FTL(Flash Transition Layer) of e·MMC manages Wear Leveling, Bad Block Management and ECC. The

FTL supports all features of the Samsung NAND flash and achieves optimal performance.

LPDDR3-SDRAM is a high-speed synchronous DRAM device internally configured as an 8-Bank memory.

This device contains the following number of bits: 4Gb has 4,294,967,296 bits

LPDDR3 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA

bus contains command, address, and bank information. Each command uses one clock cycle, during which command information is transferred on both

the positive and negative edge of the clock.

These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially

an 8n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for

the LPDDR3 SDRAM effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit

wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the LPDDR3 SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of

locations in a programmed sequence. Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command.

The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits

registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.

Prior to normal operation, the LPDDR3 SDRAM must be initialized. The following section provides detailed information covering device initialization, reg-

ister definition, command description and device operation.

The KMR8X0001M suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This

device is available in 221-ball FBGA Type.