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mpc5121e

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Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5121E

Rev. 1, 10/2008

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

MPC5121E/MPC5123

TEPBGA

27 mm x 27 mm

The MPC5121e/MPC5123 integrates a high performance

e300 CPU core based on the Power Architecture Technology

with a rich set of peripheral functions focused on

communications and systems integration.

Major features of the MPC5121e/MPC5123 are:

• e300 Power Architecture processor core (enhanced version

of the MPC603e core), operates up to 400 MHz

• Power modes include doze, nap, sleep, deep sleep, and

hibernate

• AXE – fully programmable, 200 MHz 32-bit RISC core for

real-time acceleration tasks, such as audio.

• MBX Lite – 2D/3D graphics engine with PowerVR vector

processing (only in MPC5121e, not in MPC5123)

• DIU – Display interface unit

• DDR1, DDR2, and low-power mobile DDR (LPDDR)

SDRAM memory controller

• USB 2.0 OTG controller with integrated physical layer

(PHY)

• DMA subsystem

• EMB – Flexible multi-function external memory bus

interface

• NFC – NAND flash controller

• 10/100Base Ethernet

• PCI interface, version 2.3

• PATA – Parallel ATA integrated development environment

(IDE) controller

• SATA – Serial ATA controller with integrated physical

layer (PHY)

• SDHC – MMC/SD/SDIO card host controller

• PSC – Programmable serial controller

• S/PDIF – Serial audio interface

• CAN – Controller area network

• BDLC – J1850 interface

• VIU – Video Input, ITU-656 complient

Figure 1 shows a simplified MPC5121e/MPC5123 block

diagram.

MPC5121E/MPC5123

Data Sheet

Preliminary

MPC5121E/MPC5123 Data Sheet, Rev. 1

Freescale Semiconductor2

Table of Contents

1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.1 Pinout Listings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3 Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . .16

3.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .16

3.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . .16

3.1.2 Recommended Operating Conditions . . . . . . . .17

3.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . .18

3.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . .20

3.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .22

3.1.6 Thermal Characteristics. . . . . . . . . . . . . . . . . . .23

3.2 Oscillator and PLL Electrical Characteristics . . . . . . . .24

3.2.1 System Oscillator Electrical Characteristics . . .25

3.2.2 RTC Oscillator Electrical Characteristics . . . . . .25

3.2.3 System PLL Electrical Characteristics. . . . . . . .25

3.2.4 e300 Core PLL Electrical Characteristics . . . . .26

3.3 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .27

3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.3.2 AC Operating Frequency Data. . . . . . . . . . . . . .27

3.3.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.3.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . .31

3.3.5 SDRAM (DDR) . . . . . . . . . . . . . . . . . . . . . . . . .31

3.3.6 PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.3.7 LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.3.8 NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.3.9 PATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

3.3.10 SATA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

3.3.11 FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

3.3.12 USB ULPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.3.13 On-Chip USB PHY . . . . . . . . . . . . . . . . . . . . . . 59

3.3.14 SDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.3.15 DIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.3.16 SPDIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.3.17 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.3.18 I

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.3.19 J1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.3.20 PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.3.21 GPIOs and Timers . . . . . . . . . . . . . . . . . . . . . . 72

3.3.22 Fusebox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.3.23 IEEE 1149.1 (JTAG). . . . . . . . . . . . . . . . . . . . . 73

3.3.24 VIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4 System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.1 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . 75

4.2 System and CPU Core AVDD Power Supply Filtering. 75

4.3 Connection Recommendations . . . . . . . . . . . . . . . . . . 76

4.4 Pull-Up/Pull-Down Resistor Requirements . . . . . . . . . 77

4.4.1 Pull-Down Resistor Requirements for TEST pin77

4.4.2 Pull-Up Requirements for the PCI Control Lines77

4.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.5.1 TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.5.2 e300 COP/BDM Interface . . . . . . . . . . . . . . . . 78

5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.2 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 82

6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Preliminary

剩余85页未读，继续阅读

John_Zheng

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