library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------
entity exp9 is
port( Clk : in std_logic; --ʱ������
Rst : in std_logic; -- � ����
NU,ND : in std_logic; --���룺����Ƶ ʵĸı� �
MU,MD : in std_logic; --���룺���� ȵĸıռ�ձ �
Fout : out std_logic_vector(3 downto 0) --������
a,b : in std_logic; 10%,90%ռ�ձ�
);
end exp9;
--------------------------------------------------------------------
architecture behave of exp9 is
signal N_Buffer,M_Buffer : std_logic_vector(11 downto 0);
signal N_Count :std_logic_vector(11 downto 0);
begin
process(Clk) --�������ۼ�
begin
if(Clk'event and Clk='1') then
if(N_Count>=N_Buffer) then
N_Count<="000000000000";
else
N_Count<=N_Count+1;
end if;
end if;
end process;
process(Clk) -- ���� �
begin
if(Clk'event and Clk='1') then
if(M_Buffer>=N_Count) then
Fout<="0001";
elsif(N_Count>M_Buffer) then
Fout<="0000";
end if;
end if;
end process;
process(Clk) --Ƶ ʼ ȵĸı 1� �ռ�ձ �
begin
if(Clk'event and Clk='0') then
if(Rst='0') then
M_Buffer<="010011100010";
N_Buffer<="100111000011";
elsif(NU='1') then
N_Buffer<=N_Buffer-1;
elsif(ND='1') then
N_Buffer<=N_Buffer+1;
elsif(MU='1') then
M_Buffer<=M_Buffer-1;
elsif(MD='1') then
M_Buffer<=M_Buffer+1;
if(a='1') then
M_Buffer<="000011111010";
N_Buffer<="100111000011";
if(b='1') then
M_Buffer<="100011001010";
N_Buffer<="100111000011";
end if;
end if;
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