插Ｖ的实现很简单：相当于一个序列检测器。当检测到四个连０时，用双相码１１取代第
四个０。
library ieee;
use ieee.std_logic_1164.all;
entity onev is
port(clk,clr,codein:in std_logic;
codeoutv:out std_logic_vector(1 downto 0 ));
end onev;
architecture one of onev is
signal count0:integer:=0;
begin
process(clk,clr)
begin
if (clk'event and clk='1') then
if (clr='1') then codeoutv<="00";count0<=0;
else
case codein is
when '1' => codeoutv<="01";count0<=0;
when '0' =>
if (count0=3) then codeoutv<="11";count0<=0;
else count0<=count0+1;codeoutv<="00";
end if;
when others => codeoutv<="00";count0<=count0;
end case;
end if;
end if;
end process;
end one;
插符号Ｂ的实现比较复杂点：
难点在于插入符号 B 在检测下一 V 之前，我们可以引入 4 位的移位寄存器 reg_4b 来解决难题。
library ieee;
use ieee.std_logic_1164.all;
entity twob is
port(clk,clr:in std_logic;
codeoutv:in std_logic_vector(1 downto 0);
codeoutb:out std_logic_vector(1 downto 0));
end twob;
architecture two of twob is
signal s1:std_logic_vector(3 downto 0) :="0000";
signal s0:std_logic_vector(3 downto 0) :="0000";
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