STM32L151xx，STM32L152xx和STM32L162xx的Flash和EEPROM的编程手册.pdf_stm32lhaleeprom使用

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March 2012 Doc ID 16024 Rev 5 1/50

PM0062

Programming manual

STM32L151xx, STM32L152xx and STM32L162xx

Flash and EEPROM programming

Introduction

This programming manual describes how to program the Flash memory of the

STM32L151xx, STM32L152xx and STM32L162xx medium, medium+ and high density

microcontrollers. For convenience, these are referred to as STM32L15xxx in the rest of this

document unless otherwise specified.

The Flash memory includes a program memory block, a data EEPROM block and an Option

bytes block (see Figure 1). The blocks are interfaced via a common set of control registers in

the Flash interface (FLITF).

Figure 1. Flash memory programming overview

The STM32L15xxx Flash memory can be programmed using in-circuit programming or in-

application programming.

The in-circuit programming (ICP) method is used to update the entire contents of the

Flash memory, using the JTAG, SWD protocol or the boot loader (through USART for any

STM32L1xxxx plus USB for high density device) to load the user application into the

microcontroller. ICP offers quick and efficient design iterations and eliminates unnecessary

package handling or socketing of devices.

In contrast to the ICP method, in-application programming (IAP) can use any

communication interface supported by the microcontroller (I/Os, USB, UART, I

C, SPI, etc.)

to download programming data into memory. IAP allows the user to re-program the Flash

memory while the application is running. Nevertheless, part of the application has to have

been previously programmed in the Flash memory using ICP.

The Flash interface implements instruction access and data access based on the AHB

protocol. It implements a prefetch buffer that speeds up CPU code execution. It also

implements the logic necessary to carry out Flash memory operations (Program/Erase).

Read/Write protections and option bytes are also implemented.

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Contents PM0062

2/50 Doc ID 16024 Rev 5

Contents

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.1 Relation between CPU clock frequency and Flash memory read time . 12

3.1.2 Instruction prefetch when Flash access is 64 bits . . . . . . . . . . . . . . . . . 14

3.1.3 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Memory operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Unlocking/locking memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.1 Unlocking the Data EEPROM block and the FLASH_PECR register . . 16

4.1.2 Unlocking the program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.3 Unlocking the option byte block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 Erasing memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.1 Data EEPROM word erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.2 Data EEPROM double word erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.3 Program memory page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.4 Program memory parallel page erase . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3 Programming memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.1 Program memory Fast Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.2 Program memory Half Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.3 Program memory Parallel Half Page Write . . . . . . . . . . . . . . . . . . . . . . 21

4.3.4 Data EEPROM double Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3.5 Data EEPROM Fast Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.6 Data EEPROM Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.7 Data EEPROM Fast Half Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.8 Data EEPROM Half Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.9 Data EEPROM Fast Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.10 Data EEPROM Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4 Read while write (RWW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PM0062 Contents

Doc ID 16024 Rev 5 3/50

4.4.1 Alignment error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4.2 Size error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.4.3 Bus error (Cortex-M3 hardfault or Busfault) . . . . . . . . . . . . . . . . . . . . . . 28

5 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Option byte block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Quick reference to programming/erase functions . . . . . . . . . . . . . . . . 33

7 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.1 Readout protection (RDP) of the program and data EEPROMs . . . . . . . 35

7.1.1 Level 1: memory read protection enabled . . . . . . . . . . . . . . . . . . . . . . . 35

7.1.2 Level 2: memory read protection enabled and all debug features

disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 Write protection (WRP) of the program memory . . . . . . . . . . . . . . . . . . . 37

7.3 Write protection error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.1 Access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.2 Program/erase control register (FLASH_PECR) . . . . . . . . . . . . . . . . . . . 40

9.3 Power down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . . . . . . . . . 42

9.4 Program/erase key register (FLASH_PEKEYR) . . . . . . . . . . . . . . . . . . . . 43

9.5 Program memory key register (FLASH_PRGKEYR) . . . . . . . . . . . . . . . . 43

9.6 Option byte key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . . . 44

9.7 Status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.8 Option byte register (FLASH_OBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.9 Write protection register (FLASH_WRPRx) . . . . . . . . . . . . . . . . . . . . . . . 47

9.10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

剩余49页未读，继续阅读

zdfdy

2020-12-16

有点用，可惜是英文的

yueping870

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STM32L151xx，STM32L152xx和STM32L162xx的Flash和EEPROM的编程手册.pdf

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