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Application Report
SLVA073A - July 2000
1
Power Supply Sequencing Solutions for Dual Supply
Voltage DSPs
Mixed Signal Products
ABSTRACT
This application report describes power-supply sequencing recommendations and
techniques applicable to dual supply voltage DSPs in TI’s TMS320C2000, TMS320C5000
and TMS320C6000 families. These techniques take advantage of the reset, power good,
enable and soft-start features available on TI Power Management Products, including low
drop out regulators, switching power supply controllers, supply voltage supervisors, and
power distribution switches.

SLVA073A
2
Power Supply Sequencing Solutions for Dual Supply Voltage DSPs
Contents
1 Introduction 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Core and I/O Sequencing Requirements 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Completing the Power-Up and Power-Down Operations in a Timely Manner 4. . . . . . . . . . . . . .
1.3 Sequencing the Core and I/O to Avoid System-Level Bus Contention 5. . . . . . . . . . . . . . . . . . . .
2 Core and I/O Supply Sequencing Options 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Sequencing Solutions With 3.3 V Only Available 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 P-Channel MOSFET and DC/DC Supply With Power Good 6. . . . . . . . . . . . . . . . . . . . . .
2.1.2 P-Channel MOSFET and Single SVS 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Power Distribution Switch and Power Good 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Power Distribution Switch and Single SVS 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 Power Distribution Switch and Dual SVS 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6 P-Channel MOSFET and Dual SVS 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Sequencing Solutions With Greater Than 3.3 V Available 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 LDO Voltage Regulator and Power Good 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 LDO Voltage Regulator and Single SVS 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 LDO Voltage Regulator and Dual SVS 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Sequencing Solutions With 12 V Only Available 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 References 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures
1 Dual Supplies With Bootstrap Schottky Diode 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Bus Contention on Bidirectional Port Pins 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Power Sequencing Using a P-Channel MOSFET and DC/DC With Power Good 7. . . . . . . . . . . . . . . . .
4 Power Sequencing Using a P-Channel MOSFET and Single SVS With RESET 8. . . . . . . . . . . . . . . . .
5 Power Sequencing Using the TPS2034 and Power Good Signal 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Power Sequencing Using the TPS2024 and Single SVS With RESET 12. . . . . . . . . . . . . . . . . . . . . . . . .
7 Power Sequencing Using the TPS2024 and Dual SVS With RESET 13. . . . . . . . . . . . . . . . . . . . . . . . . .
8 Power Sequencing Using a P-Channel MOSFET and Dual SVS With RESET 14. . . . . . . . . . . . . . . . . .
9 Power Sequencing Using the TPS76733 and Power-On-Reset Signal 15. . . . . . . . . . . . . . . . . . . . . . . .
10 Power Sequencing Using the TPS76733 and Single SVS With RESET 16. . . . . . . . . . . . . . . . . . . . . .
11 Power Sequencing Using the TPS76733 and Dual SVS With RESET 17. . . . . . . . . . . . . . . . . . . . . . . .
12 Power Sequencing Using a TPS5618 and TPS5633 Power Supply 19. . . . . . . . . . . . . . . . . . . . . . . . . .

SLVA073A
3
Power Supply Sequencing Solutions for Dual Supply Voltage DSPs
1 Introduction
The use of dual power supply voltages is common in TI’s high-performance DSPs. TI offers power
management products to address these power supply requirements, and those of many other
systems. This application report discusses sequencing requirements and recommendations for TI
DSPs, and presents options for sequencing power supply voltages in typical DSP applications. The
power supply solutions given in this report are intentionally left in general terms; details are given
when they are critical to a particular sequencing solution. Additional details and application reports
pertaining to components suggested can be found in the references listed at the end of the report.
Since new products are continually being developed, the user is encouraged to check the TI web
site at: http://www.ti.com
, for new products and the latest application information. In particular the
reader will find information on TI’s newly released families of advanced dual supply regulators,
TPS563xx and TPS701xx and plug-in power modules, PT693x, which specifically address
sequencing of dual supply voltage systems.
The reader is reminded that when suggestions are made, they are made in the context of a general
discussion and that the exact power supply requirements, e.g., maximum output current, output
voltage tolerance, output voltage ripple, efficiency, etc., must be considered in the power supply
selection or design process. It is also important to note that decoupling capacitors are not shown
but should be included as needed.
Many power supply configurations are possible for powering TI’s dual supply voltage DSPs,
depending on the voltage(s) available from the system for use as input power, and the configuration
of the DSP application (i.e., how many DSPs, how much other circuitry, etc.). This report addresses
sequencing solutions for the following:
• 3.3 V only available input power
• Greater than 3.3 V available input power
• 12 V only available input power (a special case of > 3.3 V)
1.1 Core and I/O Sequencing Requirements
When designing with dual supply logic devices, consideration should be given to the relative voltage
and timing of core and I/O voltage supplies during power-up and power-down operations. Internally,
the core and I/O blocks are isolated by structures which may become forward biased if the supply
voltages are not at specified levels. During the power-up and power-down operations, differences
in the starting point and ramp rates of the two supplies may cause current to flow in the isolation
structures which, when prolonged and excessive, can reduce the useable life of the semiconductor
device. These currents can also trigger latch-up in devices designed with inadequate latch-up
protection. TI DSPs tolerate a wide range of conditions during power up. However, some control of
the power-up and power-down sequencing deserves consideration to enhance short and long term
reliability of the entire system. The following note, which is included in the data sheets for dual supply
voltage DSPs, presents TI’s requirements with regard to power supply sequencing:
NOTE: TI DSPs do not require specific power sequencing between the core supply
and the I/O supply. However, systems should be designed to insure that neither
supply is powered up for extended periods of time if the other supply is below the
proper operating voltage. Excessive exposure to these conditions can adversely
affect the long term reliability of the device.

SLVA073A
4
Power Supply Sequencing Solutions for Dual Supply Voltage DSPs
System-level concerns such as bus contention may require supply sequencing to
be implemented. In this case, the core supply should be powered up at the same
time as, or prior to (and powered down after), the I/O buffers.
On C62x and C67x DSPs, during power up, it is possible for the core supply to see
a high current draw (in excess of 2A) if the core supply is powered while the I/O
supply is not. This high current is a result of uninitialized logic within the DSP. This
high current state may damage the device if the condition exists for an extended
period of time (several seconds). A normal current state will return once the I/O
power supply is turned on. Decreasing the amount of time between the core supply
power up and the I/O supply power up can minimize the effects of this current draw.
A dual power supply with simultaneous sequencing, such as available with
TPS563xx controllers or PT693x plug-in power modules, can be used to eliminate
the delay between core and I/O power up (see application note SLVA088,
Using the
TPS56300 to Power DSPs
). A Schottky diode can also be used to tie the core rail
to the I/O rail, effectively pulling up the I/O power supply to a level that can help
initialize the logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP or DSP
array to minimize inductance and resistance in the power delivery path.
Additionally, the PC board should include separate power planes for core, I/O, and
ground bypassed with high-quality, low-ESL/ESR capacitors when designing for
high performance applications, such as those with the C6x family of DSPs.
1.2 Completing the Power-Up and Power-Down Operations in a Timely Manner
When system power is applied, or when the DSP power supply system is enabled, both DSP
supplies should power up to their respective regulation points quickly. The core and I/O supplies of
a single DSP powered by a low drop-out (LDO) linear regulator will reach regulation in 100 µs or
less. A power supply capable of providing several amps to an array of DSPs typically controls the
ramp-up rate to limit in-rush currents on start-up in order to reduce stress on transistors and filter
capacitors. Slow-start or soft-start mechanisms ramp the supply in 10 ms to 100 ms nominally to
preserve supply component reliability. Bringing the core and I/O supplies to their respective
regulation levels in a maximum time frame of several hundred milliseconds, moderates the stresses
placed on both the power supply and the DSP. Including a Schottky diode, connected in an
anode-to-core and cathode-to-I/O fashion, further reduces potential stress on the C62x and C67x
DSPs by bootstrapping the I/O supply and shortening the delay between supply ramps. The
TPS563xx and PT693x products provide the most reduction by simultaneously sequencing the core
and I/O supplies, typically within 20 mV of one another. This essentially eliminates the delay in power
up of the two supplies. Figure 1 shows a simplified diagram of a bootstrap Schottky diode connected
between the I/O and core voltage regulators and a DSP.

SLVA073A
5
Power Supply Sequencing Solutions for Dual Supply Voltage DSPs
DC Input
I/O Voltage
Regulator
Core Voltage
Regulator
I/O
DV
DD
Core
CV
DD
Figure 1. Dual Supplies With Bootstrap Schottky Diode
The voltage supply rails must also discharge in several hundred milliseconds upon removal of
system power, or disabling of the DSP supply system. It is difficult to predict the power down rate
of the core and I/O supplies, since unknown factors such as the load currents drawn from each
supply during system shut down and the amount of capacitance present on each supply affect the
rate of decay. Active loads enabled during the power-down operation more predictably discharge
the core and I/O supply rails. The newest, DSP-specific, dual output LDO regulators and switching
power supply controllers from TI activate internal loads to discharge the output rails during power
down.
1.3 Sequencing the Core and I/O to Avoid System-Level Bus Contention
Of greater concern than timely power up and power down is system-level bus connection between
the I/O pins of the DSP and external peripheral devices. Power supply sequencing between the core
and I/O may be required to prevent bidirectional I/O pins of the DSP and a peripheral device from
opposing each other. Since the bus control logic originates in the core section, powering the I/O prior
to the core may result in both the DSP and peripheral pins simultaneously configured as outputs.
If the data values on each side are opposing, then the output drivers contend for control. Figure 2
shows a simple representation of bidirectional ports. Excessive current will flow in one of the paths
shown depending on the opposing data-out patterns. Following the recommendation to power the
core at the same time or before powering the I/O prevents undefined logic states on the bus control
signals.
DV
DD
Data In
Output Enable
Data Out
D0–D15
R/W
DV
DD
Data Out
Data In
Output Enable
Core I/O
Indeterminate During
CV
DD
Power Up
Core Supply DV
DD
I/O Supply DV
DD
Dual Supply Voltage DSP Peripheral
External
Bus Control
Figure 2. Bus Contention on Bidirectional Port Pins
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