FPGA的管脚类型分类和使用参考

在 fpga 芯片中支持不同 io 电平标准

2008-06-06 15:15:39| 分类： FPGA AND DSP | 标签： |字号大中小 订阅

I/O Banking

Some of the I/O standards described above require VCCO and/or VREF voltages.

These voltages are externally supplied and connected to device pins that serve groups of

IOBs, called banks. Consequently, restrictions exist about which I/O standards can be

combined within a given bank. Eight I/O banks result from separating each edge of the

FPGA into two banks (see Figure 3). The pinout tables show the bank affiliation of each

mixed only if they use the same VCCO. [在 spartan IIE 的这两种封装中，每一个 bank 的

io 电引脚是连在一起的，而参考电平引脚是在不同的 bank 中是独立的，也就是说在所有

bank 中只能有一个 io 电平，每一个 bank 可以有自己的电平。在同一个 bank 中，可以支

持不同的电平标准，但要求电平标准要相互兼容]Compatible standards are shown in

Table 2.GTL and GTL+ appear under all voltages because their open-drain outputs do

not depend on VCCO. Note that VCCO is required for most output standards and for

LVTTL,LVCMOS, and PCI inputs.

VCCO Compatible Standards

3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, LVPECL, GTL, GTL+

2.5V SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus LVDS, GTL, GTL+

each bank. All VREF pins in the bank, however, must be connected to the external

voltage source for correct operation.In a bank, inputs requiring VREF can be mixed with

those

that do not but only one VREF voltage may be used within a bank. The VCCO and

VREF pins for each bank appear in the device pinout tables. Within a given package, the

number of VREF and VCCO pins can vary depending on the size of device. In larger

devices, more I/O pins convert to VREF pins. Since these are always a superset of the

VREF pins used for smaller devices, it is