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loginid=molbasic01@ginreen.com,time=2018-03-10 16:14:07,ip=113.87.91.205,doctitle=MT6771 LTE-A Smartphone Application Processor Functional Specification V1.1.pdf,company=Ginreen_WCX

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

Version: 1.1

Release date: 2018-02-13

Specifications are subject to change without notice.

MT6771 LTE-A Smartphone Application

Processor Technical Brief

loginid=molbasic01@ginreen.com,time=2018-03-10 16:14:07,ip=113.87.91.205,doctitle=MT6771 LTE-A Smartphone Application Processor Functional Specification V1.1.pdf,company=Ginreen_WCX

MT6771

LTE-A Smartphone Application Processor

Functional Specification

Confidential A

MediaTek Confidential

Page 3 of 285

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

Table of Contents

Document Revision History ............................................................................................ 2

Table of Contents ............................................................................................................. 3

1 System Overview ................................................................................................... 10

1.1 Highlighted Features Integrated in MT6771 ......................................................................... 10

1.2 Platform Features .................................................................................................................... 12

1.3 Modem Features...................................................................................................................... 14

1.4 Connectivity Features ............................................................................................................. 16

1.5 Multimedia Features ............................................................................................................... 19

2 Product Description ............................................................................................... 21

2.1 Pin Description ........................................................................................................................ 21

2.2 Electrical Characteristic .......................................................................................................... 45

2.3 System Configuration............................................................................................................. 68

2.4 Power-on Sequence ................................................................................................................ 69

2.5 Analog Baseband .....................................................................................................................70

2.6 Package Information ............................................................................................................... 77

3 MCU and Bus Fabric ............................................................................................. 79

3.1 MCU System ............................................................................................................................ 79

3.2 On-chip Memory Controller .................................................................................................. 90

3.3 External Interrupt Controller .................................................................................................93

3.4 System Interrupt Controller ................................................................................................ 100

3.5 Infrastructure System Configuration Module ..................................................................... 103

3.6 External Memory Interface .................................................................................................. 105

3.7 DRAM Controller .................................................................................................................. 107

3.8 AP_DMA ................................................................................................................................ 113

3.9 CQ_DMA ............................................................................................................................... 116

3.10 System Companion Processor .............................................................................................. 118

3.11 System Timer ......................................................................................................................... 120

4 Clock and Power Control ..................................................................................... 123

4.1 Top Clock Generator ............................................................................................................. 123

4.2 Top Reset Generate Unit....................................................................................................... 130

4.3 Frequency Hopping Control ................................................................................................. 133

5 Peripherals .......................................................................................................... 135

5.1 Pericfg Controller .................................................................................................................. 135

5.2 GPIO ...................................................................................................................................... 137

5.3 Keypad Scanner ..................................................................................................................... 179

5.4 UART ..................................................................................................................................... 183

5.5 Super Speed Universal Serial Bus (SSUSB) ......................................................................... 186

5.6 SPI Interface Controller ........................................................................................................ 189

5.7 MSDC Controller ................................................................................................................... 193

5.8 AUXADC ............................................................................................................................... 208

5.9 I2C/SCCB Controller ............................................................................................................ 212

5.10 Pulse-Width Modulation (PWM) ......................................................................................... 217

loginid=molbasic01@ginreen.com,time=2018-03-10 16:14:07,ip=113.87.91.205,doctitle=MT6771 LTE-A Smartphone Application Processor Functional Specification V1.1.pdf,company=Ginreen_WCX

MT6771

LTE-A Smartphone Application Processor

Functional Specification

Confidential A

MediaTek Confidential

Page 4 of 285

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

5.11 General-Purpose Timer (GPT) ............................................................................................. 219

5.12 Thermal Controller................................................................................................................ 221

5.13 Audio System ........................................................................................................................ 228

5.14 Universal Flash Storage (UFS) ............................................................................................ 230

5.15 Bluetooth Interface (BTIF) .................................................................................................. 232

6 Multimedia ......................................................................................................... 235

6.1 Display Controller .................................................................................................................235

6.2 ISP .......................................................................................................................................... 237

6.3 Camera Serial Interface (CSI).............................................................................................. 238

6.4 Face Detection and Visual Tracking (FDVT) ....................................................................... 241

6.5 Vision Processor Unit (VPU) ............................................................................................... 263

6.6 DISPLAY PWM Generator .................................................................................................... 267

6.7 Display Serial Interface (DSI) ............................................................................................. 268

6.8 Digital Parallel Interface (DPI) ........................................................................................... 269

6.9 DBI ......................................................................................................................................... 272

6.10 Video Decoder (VDEC) ......................................................................................................... 275

6.11 H.264 Video Encoder ............................................................................................................ 277

6.12 MFG ....................................................................................................................................... 279

6.13 MODEM_TEMP_SHARE .................................................................................................... 281

loginid=molbasic01@ginreen.com,time=2018-03-10 16:14:07,ip=113.87.91.205,doctitle=MT6771 LTE-A Smartphone Application Processor Functional Specification V1.1.pdf,company=Ginreen_WCX

MT6771

LTE-A Smartphone Application Processor

Functional Specification

Confidential A

MediaTek Confidential

Page 5 of 285

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

Lists of Figures

Figure 1-1. High-level MT6771 functional block diagram ......................................................................... 11

Figure 2-1. LPDDR4 ball map view ............................................................................................................ 21

Figure 2-2. LPDDR3 ball map view ........................................................................................................... 22

Figure 2-3. LPDDR3 VIX definition .......................................................................................................... 52

Figure 2-4. LPDDR3 single-ended output slew-rate definition ............................................................... 53

Figure 2-5. LPDDR3 differential output slew-rate definition .................................................................. 53

Figure 2-6. LPDDR3 RX mask ................................................................................................................... 53

Figure 2-7. LPDDR4/LPDDR4X VIX definition ....................................................................................... 54

Figure 2-8. LPDDR4/LPDDR4X single-ended output slew-rate definition ........................................... 54

Figure 2-9. LPDDR4/LPDDR4X differential output slew-rate definition ............................................... 55

Figure 2-10. LPDDR4/LPDDR4X RX mask .............................................................................................. 55

Figure 2-11. SPI timing diagram ................................................................................................................ 56

Figure 2-12. I2S master mode timing diagram ......................................................................................... 56

Figure 2-13. I2C timing diagram of standard mode (100kHz) and fast mode (400kHz) ....................... 57

Figure 2-14. MSDC device input timing diagram of default speed .......................................................... 58

Figure 2-15. MSDC device output timing diagram of default speed ........................................................ 58

Figure 2-16. MSDC device input timing diagram of high speed .............................................................. 59

Figure 2-17. MSDC device output timing diagram of high speed ............................................................ 60

Figure 2-18. MSDC device clock timing diagram of SDR12/SDR25/SDR50/SDR104 mode ................ 60

Figure 2-19. MSDC device input timing diagram of SDR50/SDR104 mode ........................................... 61

Figure 2-20. MSDC device output timing diagram of fixed data window (SDR12/SDR25/SDR50) ..... 61

Figure 2-21. MSDC device output timing diagram of variable window (SDR104) .................................. 61

Figure 2-22. MSDC device clock timing diagram of DDR50 speed mode............................................... 62

Figure 2-23. MSDC device input/output timing diagram of DDR50 speed mode ................................. 63

Figure 2-24. MSDC device clock timing diagram of HS200 .................................................................... 64

Figure 2-25. MSDC device input timing diagram of HS200 .................................................................... 64

Figure 2-26. MSDC device output timing diagram of HS200 ................................................................. 64

Figure 2-27. MSDC device input timing diagram of HS400 .................................................................... 65

Figure 2-28. MSDC device output timing diagram of HS400 ................................................................. 66

Figure 2-29. Power-on sequence ............................................................................................................... 69

Figure 2-30. Block diagram of BBRX-ADC ................................................................................................ 71

Figure 2-31. Block diagram of BBTX .......................................................................................................... 72

Figure 2-32. Block diagram of ETDAC ....................................................................................................... 72

Figure 2-33. Block diagram of DETADC .................................................................................................... 73

Figure 2-34. Block diagram of APC-DAC ...................................................................................................74

Figure 2-35. Outlines and dimensions of VFBGA 11mm*11.8mm, 599-ball, 0.9mm pitch package ...... 77

Figure 2-36. Top marking of MT6771V/C .................................................................................................. 77

Figure 2-37. Top marking of MT6771V/W ................................................................................................ 78

Figure 3-1. Block diagram of on-chip memory controller ......................................................................... 91

Figure 3-2. Security memory protection scheme ...................................................................................... 92

Figure 3-3. Block diagram of external interrupt controller ..................................................................... 93

Figure 3-4. Secure view of external interrupt controller .......................................................................... 94

Figure 3-5. System interrupt controller system level block diagram ..................................................... 101

Figure 3-6. System interrupt controller architecture block diagram ..................................................... 101

Figure 3-7. DCM in action ........................................................................................................................ 104

Figure 3-8. EMI/DRAM controller top connection (LP4) ..................................................................... 106

Figure 3-9. Block diagram of DRAM controller ........................................................................................ 111