IEEE 1012-2012：核电软件质量验证与确认的权威标准

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IEEE 1012-2012是国际电气与电子工程师学会（IEEE）于2012年发布的一项官方标准，全称为《系统和软件验证与确认规范》，由软件与系统工程标准委员会（C/S2ESC）负责赞助。该标准旨在为软件和系统的开发过程提供一套详细而全面的指导，尤其是在核电行业中，它作为审查机构进行工作时的重要依据，强调了在整个软件生命周期中对产品质量的严格控制。该标准修订自IEEE 1012-2004，旨在更新和改进软件验证与确认的方法和技术，以适应快速发展的技术环境。它定义了软件验证（Verifying）和软件确认（Validating）两个关键概念，前者主要关注设计或实现阶段的正确性，确保满足预期功能；后者则着重于实际应用环境中功能、性能及安全性等方面的评估。 IEEE 1012-2012标准涵盖了软件生命周期的各个环节，包括需求分析、设计、编码、测试、集成和系统测试等，强调了每个阶段都需要进行相应的验证和确认活动。其目标是通过一套系统化的流程，确保软件产品的质量和一致性，减少潜在的风险，并提高用户对软件的信任度。在执行过程中，该标准提供了详细的操作指南，如规定了验证和确认活动的步骤、文档要求、工具选择以及风险管理方法。同时，它还倡导采用基于风险的方法，即根据软件的复杂性和重要性，确定不同阶段的验证和确认活动的优先级和深度。此外，IEEE 1012-2012标准特别强调了跨组织协作的重要性，尤其是在涉及多学科团队和多个项目阶段的情况下，确保信息共享和一致性。它还推荐了标准化的沟通和报告机制，以便在整个开发过程中跟踪和记录验证与确认活动的进展。由于该标准被授权仅限于清华大学图书馆访问，下载日期为2013年4月11日，且存在使用限制，因此它在国内软件行业内的实施和推广可能受到一定的局限。然而，作为当前软件质量控制领域的权威标准之一，IEEE 1012-2012对于提升软件质量，特别是在安全性和可靠性至关重要的领域，如核电站自动化控制系统，具有重要意义。总结来说，IEEE 1012-2012是IT行业的基石，为软件开发者、审查者和质量保证专家提供了一套实用且严谨的框架，以确保软件产品符合预期的功能和性能要求，从而提升整个行业的竞争力和可靠性。

IEEE Std 1012-2012

IEEE Standard for System and Software Verification and Validation

This standard defines the verification and validation processes that are applied to the system, software, and

hardware development throughout the life cycle, including acquisition, supply, development, operations,

maintenance, and retirement. This standard applies to the system, software, and hardware being acquired,

developed, maintained, or reused. The term software also includes firmware and microcode (e.g., Field

Programmable Gate Arrays and Programmable Logic Devices). Each of the terms system, software, and

hardware includes its associated documentation.

V&V processes consist of the Verification Process and Validation Process. The Verification Process

provides objective evidence for whether the products perform the following:

a) Conform to requirements (e.g., for correctness, completeness, consistency, and accuracy) for all

activities during each life cycle process

b) Satisfy the standards, practices, and conventions during life cycle processes

c) Successfully complete each life cycle activity and satisfy all the criteria for initiating succeeding

life cycle activities (i.e., builds the product correctly)

The Validation Process provides evidence for whether the products perform the following:

⎯ Satisfy system requirements allocated to the products at the end of each life cycle activity

⎯ Solve the right problem (e.g., correctly model physical laws, implement business rules, and use

the proper system assumptions)

⎯ Satisfy intended use and user needs in the operational environment (i.e., builds the correct

product)

The Verification Process and the Validation Process are interrelated and complementary processes that use

each other’s process results to establish better completion criteria and analysis, evaluation, review,

inspection, assessment, and test V&V tasks for each life cycle activity. The V&V task criteria described in

Table 1a through Table 1d explicitly define the conformance requirements for V&V processes.

The development of a sufficient body of evidence requires a trade-off between the amount of time spent

and a finite set of system conditions and assumptions against which to perform the V&V tasks. Each

project should define criteria for a sufficient body of evidence (i.e., selecting an integrity level establishes

one of the basic parameters), time schedule, and scope of the V&V analysis and test tasks (i.e., range of

system conditions and assumptions).

This standard does not assign the responsibility for performing the V&V tasks to any specific organization.

The analysis, evaluation, and test activities may be performed by multiple organizations; however, the

methods and purpose will differ for each organization’s functional objectives.

ISO/IEC 15288:2008 [B16] and ISO/IEC 12207:2008 [B11] require that the developer perform various

testing and evaluation tasks as an integral part of implementation. The techniques described in this standard

may be useful in performing the developer’s tests and evaluations. Therefore, whenever this standard

mentions the developer’s performance of a verification or validation activity, it is to be understood that the

reference applies to the test and evaluation tasks of implementation.

1.2 Purpose

The purpose of the standard is to perform the following:

⎯ Establish a common framework of the V&V processes, activities, and tasks in support of all

system, software, and hardware life cycle processes

⎯ Define the V&V tasks, required inputs, and required outputs in each life cycle process

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IEEE Std 1012-2012

IEEE Standard for System and Software Verification and Validation

⎯ Identify the minimum V&V tasks corresponding to a four-level integrity scheme

⎯ Define the content of the Verification and Validation Plan

1.3 Field of application

This standard applies to all applications of systems. When conducting V&V of a system, software, or

hardware element, it is important to examine the interactions with the system of which the element is a part.

This standard identifies the important system considerations that V&V processes and tasks address in

determining correctness and other V&V attributes (e.g., completeness, accuracy, consistency, and

testability).

The dynamics of complex systems and the multitude of different logic paths available within the system in

response to varying stimuli and conditions demand that the V&V effort examines the correctness of the

system for each possible variation in conditions. The ability to model complex, real-world conditions will

be limited, and thus, the V&V effort examines whether the limits of the modeling are realistic and

reasonable for the desired solution. The unlimited combination of system conditions presents the V&V

effort with the challenge of using a finite set of analytical, test, simulation, and demonstration techniques to

establish a reasonable body of evidence that the system is correct.

A system provides a capability to satisfy a stated need or objective by combining one or more of the

following: processes, hardware, software, facilities, and people. These relationships require that V&V

processes consider interactions among all system elements (software and hardware). The V&V processes

address the following interactions with the system:

⎯ Environment: Determines that the system correctly accounts for all conditions, natural

phenomena, physical laws of nature, business rules, and physical properties and the full ranges

of the system operating environment.

⎯ Operators/users: Determines that the system communicates the proper status/condition of the

system to the operator/user and correctly processes all operator/user inputs to produce the

required results. For incorrect operator/user inputs, assure that the system is protected from

entering into a dangerous or uncontrolled state. Validate that operator/user policies and

procedures (e.g., security, interface protocols, data representations, and system assumptions) are

consistently applied and used across each component interface.

⎯ Other software, hardware and systems: Determines that the software or hardware component

interfaces correctly with other components in the system in accordance with requirements and

that errors are not propagated between components of the system.

The scope of V&V processes includes the operational environment, operators and users, hardware,

software, data processes (e.g., processes for providing service to users), procedures (e.g., operator

instructions), and facilities. The user of this standard should consider V&V as part of the life cycle

processes defined by industry standards, such as ISO/IEC 12207:2008 [B11], IEEE Std 1074-2006 [B9], or

ISO/IEC 15288:2008 [B16].

To address the systems perspective, system, software, and hardware V&V effort should provide an

integrated analysis where the V&V tasks are interrelated, providing input and insight into other V&V tasks.

The results from completed life cycle processes provide valuable and necessary inputs to V&V tasks in

other life cycle processes. The results and findings from one V&V task may cause previously completed

V&V tasks to be analyzed again with the new data. This relationship among V&V tasks (including

feedback to the Technical and Software/Hardware Specific Processes) employing rigorous systems

engineering techniques is a key approach to an integrated systems, software, and hardware V&V. The

V&V results provide the other processes with an early detection of anomalies and potential process trends

that may be used for process improvement. The V&V processes and tasks described in this standard may be

used in conjunction with systems engineering and process improvement models, such as the

CMU/SEI-2010-TR-033 [B1].

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IEEE Std 1012-2012

IEEE Standard for System and Software Verification and Validation

1.4 V&V objectives

V&V processes provide an objective assessment of products and processes throughout the life cycle. This

assessment demonstrates whether the requirements are correct, complete, accurate, consistent, and testable.

The V&V processes determine whether the products of a given activity conform to the requirements of that

activity and whether the product satisfies its intended use and user needs. The determination includes

assessment, analysis, evaluation, review, inspection, and testing of products and processes. V&V tasks shall

be performed in parallel with all life cycle stages, not at their conclusion.

The results of V&V provide the following benefits to the program:

⎯ Facilitate early detection and correction of anomalies

⎯ Enhance management insight into process and product risks

⎯ Support the life cycle processes to assure conformance to program performance, schedule, and

budget

⎯ Provide an early assessment of performance

⎯ Provide objective evidence of conformance to support a formal certification process

⎯ Improve the products from the acquisition, supply, development, and maintenance processes

⎯ Support process improvement activities

1.5 Organization of the standard

This standard is organized into clauses (Clause 1 through Clause 12), tables (Table 1 through Table 3, and

their respective subparts a–d), figures (Figure 1 and Figure 2, and their respective subparts a–d), and

annexes (Annex A through Annex M). Clause 2 through Clause 12 and Table 1a through Table 1d and

Table 2a through Table 2d provide the mandatory V&V requirements for this standard. Table 1a through

Table 1d and Table 2a through Table 2d are the focal point of this standard, containing detailed V&V

activity and task requirements. Table 1a through Table 1d and Table 2a through Table 2d are broken into

four subtables:

⎯ Common V&V tasks in Table 1a and Table 2a

⎯ System V&V tasks in Table 1b and Table 2b

⎯ Software V&V tasks in Table 1c and Table 2c

⎯ Hardware V&V tasks in Table 1d and Table 2d

Each clause containing V&V activities and tasks has the subset of Table 1a through Table 1d and Table 2a

through Table 2d associated with the V&V requirements for that clause. Figure 1a through Figure 1d,

Figure 2a through Figure 2d, and Table 3a through Table 3d contain informative material that provides

examples of V&V processes and provides guidance for using this standard, and they are similarly

organized. All annexes are informative.

⎯ Clause 1 provides guidance for using this standard.

⎯ Clause 2 is reserved for normative references; however, this standard does not prescribe any

normative references.

⎯ Clause 3 provides a definition of terms, abbreviations, and conventions.

⎯ Clause 4 describes the relationships between the V&V processes and the life cycle processes

from ISO/IEC 15288:2008 [B16] and ISO/IEC 12207:2008 [B11], and it describes how the

V&V standard is applied recursively within the concept of a system of systems and from system

to software or hardware components.

⎯ Clause 5 describes the use of integrity levels to determine the scope and rigor of V&V

processes.

⎯ Clause 6 explains how V&V tasks are described within this standard.

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IEEE Std 1012-2012

IEEE Standard for System and Software Verification and Validation

⎯ Clause 7 describes common V&V tasks; that is, tasks that are common across application of this

standard to system, software, or hardware.

1) Table 1a contains the V&V tasks and activities and their criteria for common V&V

tasks and activities.

2) Table 2a contains the minimum tasks for each integrity level for common V&V tasks.

3) Table 3a contains the optional common V&V tasks.

4) Figure 1a depicts a summary of common V&V activities and tasks.

5) Figure 2a depicts a summary of V&V test products and tasks.

⎯ Clause 8 describes system V&V tasks.

1) Table 1b contains the V&V tasks and activities and their criteria for system V&V tasks

and activities.

2) Table 2b contains the minimum tasks for each integrity level for system V&V tasks.

3) Table 3b contains the optional system V&V tasks.

4) Figure 1b depicts a summary of system V&V activities and tasks

5) Figure 2b depicts a summary of system V&V test products and tasks

⎯ Clause 9 describes software V&V tasks.

1) Table 1c contains the V&V tasks and activities and their criteria for software V&V

tasks and activities.

2) Table 2c contains the minimum tasks for each integrity level for software V&V tasks.

3) Table 3c contains the optional software V&V tasks.

4) Figure 1c depicts a summary of software V&V activities and tasks.

5) Figure 2c depicts a summary of software V&V test products and tasks.

⎯ Clause 10 describes hardware V&V tasks.

1) Table 1d contains the V&V tasks and activities and their criteria for hardware V&V

tasks and activities.

2) Table 2d contains the minimum tasks for each integrity level for hardware V&V tasks.

3) Table 3d contains the optional hardware V&V tasks.

4) Figure 1d depicts a summary of hardware V&V activities and tasks.

5) Figure 2d depicts a summary of hardware V&V test products and tasks.

⎯ Clause 11 describes V&V reporting, administrative, and documentation requirements.

⎯ Clause 12 describes the content of a V&V plan.

This standard is organized so that the V&V processes (system, software, or hardware) may be invoked

separately or in any combination. V&V processes may be accomplished in any of the following

combinations: system V&V (Clause 8), software V&V (Clause 9), hardware V&V (Clause 10),

system/software V&V (Clause 8 and Clause 9), system/hardware V&V (Clause 8 and Clause 10),

software/hardware V&V (Clause 9 and Clause 10), and system/software/hardware V&V (Clause 8 through

Clause 10). Some V&V tasks are common to systems, software, and hardware V&V; in order not to repeat

these V&V tasks in each part, the common V&V tasks are listed once in Clause 7. The common V&V tasks

are invoked for any V&V that is performed. These combinations are illustrated in Figure 3.

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IEEE Std 1012-2012

IEEE Standard for System and Software Verification and Validation

V&V Scope Common System Software Hardware

System only X X

Software only X X

Hardware only X X

System and software X X X

System and hardware X X X

Software and hardware X X X

System, software, and hardware X X X X

Figure 3 —V&V effort combinations

NOTE—References to Table 1 and Table 2 without a suffix a, b, c, or d are understood to include those parts of the

table that correspond to the parts of the V&V scope being invoked (i.e., Common, System, Software, or Hardware).

References to Figure 1 and Figure 2 that do not have a suffix a, b, c, or d are similarly understood to include those parts

of the figure that correspond to the parts of the V&V scope being invoked.

Clause 4 through Clause 6 contain guidance that is applicable to all combinations of the V&V scope.

Clause 11 contains reporting requirements for all combinations of V&V scope. Clause 12 contains a sample

V&V plan.

Table 1a through Table 1d provide V&V task descriptions, inputs, and outputs for each life cycle process.

Table 2a through Table 2d list minimum V&V tasks required for different integrity levels. Table 3a through

Table 3d provide a list of optional V&V tasks and their suggested applications in the system life cycle.

These optional V&V tasks may be added to the minimum V&V tasks to tailor the V&V effort to project

needs.

Figure 1a through Figure 1d provide an example of an overview of the V&V inputs, outputs, and minimum

V&V tasks for integrity level 4. Figure 2a through Figure 2d provide guidelines for scheduling V&V test

planning, execution, and verification activities. An example of a phased life cycle model was used in

Figure 1a through Figure 1d and Figure 2a through Figure 2d to illustrate a mapping of the

ISO/IEC 12207:2008 [B11] life cycle processes to the V&V activities and tasks described in this standard.

Annex A describes the mapping of ISO/IEC 12207:2008 [B11] and ISO/IEC 15288:2008 [B16] to this

standard’s V&V activities and tasks. Annex B provides an example of a risk-based, four-level integrity

scheme. Annex C provides a definition of independent verification and validation (IV&V). Annex D

provides guidelines for conducting V&V of reuse software. Annex E describes V&V measures. Annex F

illustrates an example of the V&V organizational relationship to other project responsibilities. Annex G

describes optional V&V tasks. Annex H describes environmental factors that should be considered when

conducting V&V. Annex I discusses potential issues with interactions among system, software, and

hardware. Annex J describes hazard analysis, security analysis, and risk analysis and their role in V&V.

Annex K provides an example of assigning and changing the integrity level of supporting system functions.

Annex L maps the process outcomes from ISO/IEC 12207:2008 [B11] and ISO/IEC 15288:2008 [B16] to

associated V&V tasks. Annex M provides a bibliography of the informative standards referenced in this

standard.

1.6 Audience

The audience for this standard includes system, software, and hardware suppliers, acquirers, developers,

maintainers, V&V practitioners, operators, users, and managers in both the supplier and acquirer

organizations.

Notes in text, tables, and figures of a standard are given for information only and do not contain requirements needed to implement

this standard.

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