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首页IT6604&6605; Programming Guide.1.01
IT6604&6605; Programming Guide.1.01
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IT6604&6605;编程手册,此文档主要阐述芯片寄存器配置相关内容,配合相应的datasheet,即可满足该芯片开发所需。
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ITE Confidential
For Movidius Only
IT6605 HDMI 1.4 3D Receiver
Programming Guide
Ver 1.01
Tseng, Jau-Chih
ITE Tech.
Last Update Date: 2011/03/02
ITE Confidential
For Movidius Only
History
2010/08/10 – Created by Tseng, Jau-chih
2010/08/11 – Added Audio Part.
2010/12/07 – Added HDCP part.
ITE Confidential
For Movidius Only
-i
Index
Chap 1 Introduction ..................................................................................................................1
Chap 2 Initial Progress .............................................................................................................2
Initial Progress..............................................................................................................................................2
Initial Value List ...........................................................................................................................................2
Chap 3 Video Output.................................................................................................................4
Video Output Flow .......................................................................................................................................4
Video Path ....................................................................................................................................................5
Video Input Selection ...................................................................................................................................5
Video Output Configuration .........................................................................................................................6
Color Space Matrix.......................................................................................................................................7
Video I/O and Video Data I/O Tristate..........................................................................................................8
Event of Video Process.............................................................................................................................9
Video input mode resolution.......................................................................................................................10
Video CDR Reset........................................................................................................................................10
Chap 4 Audio Output...............................................................................................................11
Audio Control Registers ............................................................................................................................. 11
HDMI Audio Input Status...........................................................................................................................12
Audio Output Configure.............................................................................................................................13
Default Setting .......................................................................................................................................13
I2S mode and word length......................................................................................................................13
Output LPCM Audio on I2S Channel.........................................................................................................14
Output LPCM Audio on SPDIF Channel....................................................................................................14
Output NLPCM Audio on I2S Channel......................................................................................................14
Output NLPCM Audio on SPDIF Channel.................................................................................................15
Output High Bit Rate on I2S Channel ........................................................................................................15
Output High Bit Rate on SPDIF Channel...................................................................................................15
Output LPCM/NLPCM Audio with Force Fs setting..................................................................................15
Error Handling............................................................................................................................................16
Chap 5 HDMI Infoframe.........................................................................................................17
Chap 6 HDCP Support............................................................................................................19
HDCP Repeater setting...............................................................................................................................19
HDCP registers for repeater function .....................................................................................................21
HDCP Debug Status...............................................................................................................................22
Chap 7 3D Support..................................................................................................................23
Part 2 – Software Release Code Reference.....................................................................................26
Chap 8 Introduce.....................................................................................................................26
Chap 9 Flow............................................................................................................................27
Chap 10 Data Type....................................................................................................................30
Chap 11 Sample Code Required Interface ................................................................................31
Chap 12 Software Interface.......................................................................................................32
ITE Confidential
For Movidius Only
IT6605 PROGRAMMING GUIDE
ITE Tech.
-1- 2011/03/02
Chap 1 Introduction
The IT6605 is a dual-port HDMI 1.4 receiver. The IT6605 with its Deep Color capability (up to 36-bit)
ensures robust reception of high-quality uncompressed video content, along with state-of-the-art
uncompressed and compressed digital audio content such as DTS-HD and Dolby TrueHD in digital
televisions and projectors.
Aside from the various video output formats supported, the IT6605 also receives and provides up to 8
channels of I
2
S digital audio outputs, with sampling rate up to 192kHz and sample size up to 24 bits,
facilitating direct connection to industry-standard low-cost audio DACs. Also, an S/PDIF output is
provided to support up to compressed audio of 192kHz frame rate. Super Audio Compact Disc (SACD)
is supported at up to 8 channels and 88.2kHz through DSD (Direct Stream Digital ports) ports.
Each IT6605 comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.2
standard so as to provide secure transmission of high-definition content. Users of the IT6605 need not
purchase any HDCP keys or ROMs.
To program IT6605 need using I
2
C access the PCSDA (pin26) and PCSCL (pin27) with the frequency
under 100KHz. The I
2
C address for accessing internal registers are 0x90 or 0x92 depends on the
PCADR (pin105) value.
To access the IT6605 internal registers should by the following protocol:
Read:
<I
2
C start>-<0x90|w >-<register index>-<I
2
C repeater start>-<0x90|r>-<data>(-…-<data>)-<I
2
C Stop>
Write:
<I
2
C start>-<0x90|w >-<register index>-<data>(-…-<data>)-<I
2
C Stop>
In the following document, the register with index will present as Reg<idx>.
Eg: Reg05 means the register with index 0x05.
ITE Confidential
For Movidius Only
IT6605 PROGRAMMING GUIDE
ITE Tech.
-2- 2011/03/02
Chap 2 Initial Progress
The first step of initial IT6605 is to reset the chip.
Activate SYSRSTN (pin100) with low voltage or write reg05[4] = ‘1’, will reset the chip.
When SYSRSTN is high voltage and reg05[4] = ‘0’, IT6605 is under normal operating mode.
Initial Progress
Set HPD (HDMI Connection Pin19) to low (if possible).
Reg06 = 0x00 to power on all modules.
Reg07[3:2] = ‘11’ to turn off the termination.
Reg05 = 0xA1
Reg16 = 0x0F
Reg17 = 0x07
Reg18 = 0x07
Reg8C = 0x00 (5~8 is for initial interrupt mask setting)
Load the default value.
Configure the HDCP repeater setting
Receiver mode, reg73[7:4] = ‘0000’
Repeater mode, reg73[7:4] = ‘1000’
Delay about 500ms to make sure the HPD off enough.
Reg07[3:2] = ‘00’
Set HPD to high (if possible).
Initial Value List
reg05 = 0x20
reg08 = 0xAE
reg1D = 0x20
reg3B=0x40
reg56=0x01
reg68=0x03
reg6B=0x11
Reg6C=0x00
Reg93=0x43
Reg94=0x4F
Reg95=0x87
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