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更新于2023-03-16
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PC43XX的usermannual本来是集成了所有芯片的功能介绍,但是周立功的中文资料只有LPC4330,将LPC4370中有关高速AD的部分给删去,让我们想搞这部分的人士很是头痛,这里帮你解决
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UM10503
LPC43xx ARM Cortex-M4/M0 multi-core microcontroller
Rev. 1.7 — 17 October 2013 User manual
Document information
Info Content
Keywords LPC43xx, LPC4300, LPC4370, LPC4350, LPC4330, LPC4320, LPC4310,
LPC4357, LPC4353, LPC4337, LPC4333, LPC4327, LPC4325, LPC4323,
LPC4322, LPC4317, LPC4315, LPC4313, LPC4312, ARM Cortex-M4, ARM
Cortex-M0, SPIFI, SCT, USB, Ethernet, LPC4300 user manual, LPC43xx
user manual
Abstract LPC4300 user manual
UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 1.7 — 17 October 2013 2 of 1416
NXP Semiconductors
UM10503
LPC43xx User manual
Revision history
Rev Date Description
1.7 20131017 LPC43xx User manual
Modifications: • 12-bit ADC (ADCHS) for parts LPC4370 added. See Chapter 47.
• Table 45 “LPC43xx part identification numbers” updated.
• BASE_APLL_CLK renamed to BASE_AUDIO_CLK in Chapter 12 “LPC43xx Clock Generation Unit
(CGU)”, Chapter 13 “LPC43xx Clock Control Unit (CCU)”, Chapter 10 “LPC43xx Configuration
Registers (CREG)”, and Chapter 43 “LPC43xx I2S interface”.
• Core M0SUB added for parts LPLC4370. See Chapter 2 “LPC43xx Multi-Core configuration and
Inter-Process Communication (IPC)”, Chapter 12 “LPC43xx Clock Generation Unit (CGU)”,
Chapter 13 “LPC43xx Clock Control Unit (CCU)”, Chapter 10 “LPC43xx Configuration Registers
(CREG)”, Chapter 14 “LPC43xx Reset Generation Unit (RGU)”, and Chapter 3 “LPC43xx Memory
mapping”.
• Power-down mode with M0SUB SRAM maintained added for parts LPC4370. See Chapter 11
“LPC43xx Power Management Controller (PMC)” and Table 115.
• AES speed corrected. See Section 7.2.
• Bit description of register CREG5 corrected. Bits 9:0 changed to reserved. Use bits 12:10 for
disabling JTAG. See Section 10.4.3 “CREG5 control register”
.
• Description of the RESET pin updated in Section 15.2 “Pin description”.
• Use of EMC_CLK pins clarified for SDRAM devices. See Section 22.2.
• Pin description of the RESET pin updated. See Chapter 15
• Pin description of pins SD_VOLTD[2:0] updated in Table 352.
• Add bits 20 (BOD reset) and 21 (reset after wake-up from deep power-down) to the event router
registers. See Ta ble 8 0
, Tab l e 83 to Ta b le 91 .
• Table 200 “SD/MMC delay register (SDDELAY, address 0x4008 6D80) bit description” added.
• USB driver code listing corrected. See Section 26.5 “USB API”.
• Register RESET_EXT_STAT4 removed. See Table 167.
• SDRAM address mappings added in Table 430.
• Device MX25L6435EM2I-10G added to Table 24 “QSPI devices supported by the boot code and the
SPIFI API”.
• Table 4 “Ordering options” corrected. ULPI not available on 144-pin and 100-pin packages.
• Editorial updates to Section 5.3.5 “Boot image creation” and Figure 16 “Image encryption flow”
added.
• Editorial edits to Chapter 7 “LPC43xx Security API”. Section “CMAC using AES hardware
acceleration” removed.
• VADC replaced by ADCHS throughout the document.
• Section 12.2.1 “Configuring the BASE_M4_CLK for high operating frequencies” corrected to ensure
safe operation of the clock ramping procedure.
• Figures and tables in Section 43.7.2 “I2S operating modes” corrected.
UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 1.7 — 17 October 2013 3 of 1416
NXP Semiconductors
UM10503
LPC43xx User manual
Modifications: • LPC4320 and LPC4310 part IDs corrected. See Table 45 “LPC43xx part identification numbers” and
the LPC4350/30/20/10 errata sheet.
• Description of word1 of the part id corrected. See Table 45 “LPC43xx part identification numbers”.
• General description of the OTP updated. See Section 4.3.
• General description of the AES updated. See Section 7.3.
• Figure 14 “Boot process for parts without flash” updated.
• Figure 115 “Repetitive Interrupt Timer (RIT) block diagram” corrected.
• Details about encryption of the image header added in Section 5.3.4 “Boot image header format”.
• Figure 14 “Boot process for parts without flash” corrected. SPI(SSP) boot requires image header.
• Bit description of Table 378 “Debounce Count Register (DEBNCE, address 0x4000 4064) bit
description” updated. Host clock is the SD_CLK clock.
• Security features updates. FIPS compliancy added. See Section 7.2.
• ISP mode added to Figure 14 “Boot process for parts without flash”.
• Reset values of the EEPROM RWSTATE and WSTATE registers updated. See Table 1153.
• AES API function offsets corrected. See Ta bl e 73 .
• Part MX25L8006EM2L-12GMX25L8035E, MX25L1633E, MX25L3235E, MX25L6435E,
MX25L12835F, MX25L25635F added to list of devices supported for SPIFI boot. See Table 24
.
1.6 20130125 LPC43xx user manual.
Modifications:
• SGPIO-DMA connections clarified. See Figure 10 and Figure 11.
• SGPIO location corrected in Figure 1 and Figure 3.
• SGPIO added to DMA master 0. See Section 19.4 and Section 18.4.1.
• GPIO group interrupt wake-up from power-down modes corrected in Section 17.3.2. Only wake-up
from sleep mode supported.
• Section 5.3.6.4.1 “Supported QSPI devices” moved to Chapter 5 “LPC43xx Boot ROM”.
• SPIFI register map and register descriptions added in Chapter 22 “LPC43xx SPI Flash Interface
(SPIFI)”.
• Bit description of Table 987 “CAN error counter (EC, address 0x400E 2008 (C_CAN0) and 0x400A
4008 (C_CAN1)) bit description” corrected.
• Bit clock calculation and bit description corrected in Section 43.6.1.4 “CAN bit timing register”.
1.5 20121203 LPC43xx user manual.
Revision history …continued
Rev Date Description
UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 1.7 — 17 October 2013 4 of 1416
NXP Semiconductors
UM10503
LPC43xx User manual
Modifications • Statement regarding the connection between sampling pin P2_7 and the watchdog timer overflow bit
is incorrect and was removed in Section 47.4.1 “Sampling of pin P2_7” and Figure 176 “Boot process
flowchart for LPC43xx parts with flash”.
• SCT alias register locations corrected in Table 648.
• IRC accuracy corrected for flash-based parts. See Section 1.2.
• SCT with dither engine added for flash-based parts.
• SGPIO DMA connections added in Table 45 “DMA mux control register (DMAMUX, address 0x4004
311C) bit description”.
• Section 26.6.2 “MAC Frame filter register” updated to include hash filter option.
• Section 26.7.1 “Hash filter” with examples added.
• Description of the I2C MASK register clarified (see Section 44.7.10).
• Description of the I2C slave address updated in Section 44.7.8.
• UART1 TER register location and bit description corrected. See Table 902.
• Polarity of the DMACSYNC bit in the GPDMA SYNC register corrected (see Table 285).
• SGPIO pattern match example corrected. See Section 18.7.3.
• OTP API function table corrected. Location 0x1C is reserved. See Table 16.
• SPIFI data rate and maximum clock corrected to SPIFI_CLK = 104 MHz and 52 MB/s.
• Parts LPC433x, LPC432x, and LPC431x added.
• The following changes were made on the TFBGA180 pinout in Table 128:
– P1_13 moved from ball D6 to L8.
– P7_5 moved from ball C7 to A7.
– PF_4 moved from ball L8 to D6.
– RESET
moved from ball B7 to C7.
– RTCX2 moved from ball A7 to B7.
– Ball G10 changed from VSS to VDDIO.
• Section 49.9 “JTAG TAP Identification” updated.
• EMC Configuration register, bit 8 changed to reserved. See Table 356 “EMC Configuration register
(CONFIG - address 0x4000 5008) bit description”.
• Dual-core power-down modes added to Chapter 10 “LPC43xx Power Management Controller
(PMC)”.
Revision history …continued
Rev Date Description
UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 1.7 — 17 October 2013 5 of 1416
NXP Semiconductors
UM10503
LPC43xx User manual
Modifications: • ETM time stamping feature not implemented. See Chapter 49.
• Bit 0 in the RGU RESET_STATUS0 register changed to reserved. Section 13.5.1 “Determine the
cause of a core reset” added.
• Micron part N25Q256 removed from the list of devices supported by the SPIFI boot ROM driver and
API. (See Table 387 “QSPI devices not supported by the boot code”.) Section 22.6 updated.
• Part S25FL129P0XNFI01 added to the list of devices supported by the SPIFI boot ROM driver.
• SGPIO register descriptions for CTRL_ENABLED and CTRL_DISABLED registers updated (see
Table 230 and Table 231).
• Section 21.7.5 “Dynamic Memory Refresh Timer register” register description updated.
• Description of the Motor control PWM INVDC bit updated in Table 734 “MCPWM Control read
address (CON - 0x400A 0000) bit description”.
• Description of the Alarm timer PRESETVAL bit updated in Table 799 “Preset value register (PRESET
- 0x4004 0004) bit description”.
• Description of ADC pins on digital/analog input pins changed. Each input to the ADC is connected to
ADC0 and ADC1. See Table 128, Table 129, Table 1040, and Section 15.1.
• Description of extra status bits added to Table 568 “DMA Status register (DMA_STAT, address
0x4001 1014) bit description”.
• Use of lower SPIFI memory clarified in Table 384 “SPIFI flash memory map”.
• Description of DAC DMA_ENA bit clarified in Table 1054 “D/A Control register (CTRL - address
0x400E 1004) bit description”.
• Pseudo-code for PLL registers updated by code snippets from LPC43xx sample code in Chapter 11.
• Reset delay clock cycles explained in Section 13.4.1 “RGU reset control register”.
1.4 20120903 LPC43xx user manual.
Modifications: • SSP0 boot pin functions corrected in Table 18 and Table 19. Pin P3_3 = SSP0_SCK, pin P3_6 =
SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.
• CLKMODE3 removed from the SCT. Bit value CLKMODE = 0x3 changed to reserved in Table 647
“SCT configuration register (CONFIG - address 0x4000 0000) bit description”.
• SWD mode removed for ARM Cortex-M0.
• Details for GIMA clock synchronization added in Section 16.3.2.
• RESET_EXT_STATUS0 register removed in Chapter 13.
• Reset value of BASE_SAFE_CLK register changed to R (read-only) in Table 84.
• Reset delay values corrected in Figure 31 “RGU Reset structure”.
• RGU reset values corrected in Table 113 “Register overview: RGU (base address: 0x4005 3000)”.
• Editorial updates in Chapter 18 “LPC43xx Serial GPIO (SGPIO)”.
• POR reset value of the event router STATUS register corrected in Table 31 and Table 37.
• USB boot mode updated: 12 MHz external crystal required. See Section 5.3.5.5.
• IAP invoke call entry pointer clarified in Section 46.8.
• EMC memory data and control lines clarified for the LQFP208 package in Table 349.
• Figure 11 updated to include boot process for AES capable parts.
• Editorial updates.
Revision history
…continued
Rev Date Description
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