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首页PCIExpressArchitectureConfigurationSpaceTestSpecificationRevision3.0.pdf
This document primarily covers PCI Express testing of all defined PCI Express Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification and Chapter 7 of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). This specification does not describe the full set of PCI Express tests for these devices. In particular, devices must also meet the requirements and tests described in the latest versions of the following documents as well as any other tests provided by the PCI-SIG:
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PCI Express Architecture Configuration Space, Revision 3.0 1
PCI Express Architecture
Configuration Space
Test Specification
Revision 3.0
June 6, 2013
PCI EXPRESS ARCHITECTURE CONFIGURATION SPACE TEST SPECIFICATION, REV. 3.0
PCI-SIG
®
disclaims all warranties and liability for the use of this document and the information contained herein and assumes no
responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information
contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
Questions regarding this specification or membership in PCI-SIG may be forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
Phone: 503-619-0569
Fax: 503-644-6708
Technical Support
techsupp@pcisig.com
DISCLAIMER
This PCI Code and ID Assignment Specification is provided as is with no warranties whatsoever, including any warranty of
merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal,
specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this
specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
PCI Express is a trademark of PCI-SIG.
All other product names are trademarks, registered trademarks, or service marks of their respective owners.
© 2012, 2013 PCI SIG. All rights reserved.
2
Revision
Revision History
Date
1.0 Initial release.1.0 Release 04/26/2004
1.1 Updated for PCI Express 1.1 test updates/additions. 12/03/2006
2.0 Updated for PCI Express 2.0. 08/25/2008
2.0a
Updated to include 2.0 Test Specification errata and
changes in the Errata for the PCI Express Base
Specification Revision 2.0 document. Also
typographical, grammatical, and formatting errors
were corrected.
06/19/2009
3.0 Updated for PCI Express 3.0.
Added tests for ATS, and SR-IOV specifications.
Obsoleted some motherboard-specific tests.
03/20/2013
PCI Express Architecture Configuration Space, Revision 3.0 3
Contents
1. INTRODUCTION .............................................................................................. 6
1.1. DOCUMENT CONVENTIONS ......................................................................................................... 6
1.2. COVERAGE .................................................................................................................................... 7
1.3. TEST OPTIONS FOR SPECIFICATION REVISIONS ............................................................................ 8
1.4. FUNCTION UNDER TEST DISCOVERY ............................................................................................ 9
1.4.1. Discovery of Basic Functions, ARI Functions, Base Functions,
Physical Functions, and Virtual Functions .................................................................... 9
2. TEST DESCRIPTIONS ..................................................................................... 13
2.1. COMMON PROCEDURES AND ROUTINES ................................................................................... 13
2.1.1. Standard Initialization Procedure ............................................................................... 13
2.1.2. Standard Register Field Characteristic Test Routines ................................................. 21
2.2. CONFIGURATION REGISTER TESTS (ALL DEVICES) ...................................................................... 43
2.2.1. TD_1_2 PCI Express Capability Structure .................................................................... 43
2.2.2. TD_1_3 PCI Express Capabilities Register ................................................................... 45
2.2.3. TD_1_4 Device Capabilities, Device Control, and Device Status Registers ................. 47
2.2.4. TD_1_40 Device Capabilities 2, Device Control 2, and
Device Status 2 Registers (PCIe Cap Ver = 2) .............................................................. 51
2.2.5. TD_1_5 Link Capabilities, Link Control, and Link Status Registers ............................. 57
2.2.6. TD_1_41 Link Capabilities 2, Link Control 2, and Link Status 2 Registers
(PCIe Cap Ver = 2) ....................................................................................................... 62
2.2.7. TD_1_49 Slot Capabilities, Slot Control, and Slot Status Registers
(PCIe Cap Ver = 2) ....................................................................................................... 68
2.2.8. TD_1_50 Slot Capabilities 2, Slot Control 2, and Slot Status 2 Registers
(PCIe Cap Ver = 2) ....................................................................................................... 73
2.2.9. TD_1_51 Root Capabilities, Root Control, and Root Status Registers
(PCIe Cap Ver = 2) ....................................................................................................... 74
2.2.10. TD_1_6 MSI Capability Structure................................................................................ 77
2.2.11. TD_1_7 Advanced Error Reporting Extended Capability Structure ............................ 79
2.2.12. TD_1_8 Virtual Channel Extended Capability Structure ............................................. 99
2.2.13. TD_1_9 Device Serial Number Extended Capability Structure ................................. 104
2.2.14. TD_1_10 Power Budgeting Extended Capability Structure ...................................... 105
2.2.15. TD_1_11 Command and Status Registers ................................................................ 109
2.2.16. TD_1_12 Cache Line Size, Master/Primary Latency Timer, and
Min_Gnt/Max_Lat Registers .................................................................................... 111
2.2.17. TD_1_13 Interrupt Pin and Interrupt Line Registers ................................................. 113
2.2.18. TD_1_14 Secondary Latency Timer and Secondary Status Registers ....................... 114
2.2.19. TD_1_15 Bridge Control Register ............................................................................. 116
2.2.20. TD_1_16 PCI Power Management Capability Structure ........................................... 118
2.2.21. TD_1_17 MSI-X Capability Structure ........................................................................ 124
2.2.22. TD_1_18 Base Address Registers.............................................................................. 127
2.2.23. TD_1_19 Multi-Function Virtual Channel Extended Capability Structure ................ 130
2.2.24. TD_1_52 Vendor Specific Capability Structure ......................................................... 135
2.2.25. TD_1_20 Vendor-Specific Extended Capability Structure ......................................... 136
PCI Express Architecture Configuration Space, Revision 3.0 4
2.2.26. TD_1_21 BIST Register ............................................................................................. 138
2.2.27. TD_1_22 Slot Numbering Capability Structure ......................................................... 140
2.2.28. TD_1_53 SSID/SSVID Capability Structure ................................................................ 141
2.2.29. TD_1_23 PCI Next Capability Pointer Register ......................................................... 143
2.2.30. TD_1_24 PCI Express Next Extended Capability Pointer Register ............................ 144
2.2.31. TD_1_25 Misc Type 0 Config Space Header Registers .............................................. 145
2.2.32. TD_1_26 Misc Type 1 Config Space Header Registers .............................................. 148
2.2.33. TD_1_27 Multi-Function ........................................................................................... 155
2.2.34. TD_1_28 Vital Product Data Capability Structure .................................................... 162
2.2.35. TD_1_32 PCI-X Capability Structure ......................................................................... 165
2.2.36. TD_1_30 Root Complex Link Declaration Extended Capability Structure ................ 168
2.2.37. TD_1_31 Root Complex Internal Link Control Extended Capability Structure .......... 172
2.2.38. TD_1_34 RCRB Header Extended Capability Structure ............................................. 175
2.2.39. TD_1_29 Root Complex Event Collector Endpoint Association Extended
Capability Structure .................................................................................................. 177
2.2.40. TD_1_35 Configuration Access Correlation Extended Capability Structure ............. 179
2.2.41. TD_1_39 Function Level Reset .................................................................................. 180
2.2.42. TD_1_42 ACS Extended Capability Structure ............................................................ 183
2.2.43. TD_1_43 ARI Extended Capability Structure ............................................................ 186
2.2.44. TD_1_44 DPA Extended Capability Structure ........................................................... 189
2.2.45. TD_1_45 Resizable BAR Extended Capability Structure ........................................... 192
2.2.46. TD_1_46 Multicast Extended Capability Structure ................................................... 196
2.2.47. TD_1_47 LTR Extended Capability Structure ............................................................ 199
2.2.48. TD_1_48 TPH Requester Extended Capability Structure .......................................... 201
2.2.49. TD_1_54 ATS Extended Capability Structure ............................................................ 204
2.2.50. TD_1_55 Page Request Extended Capability Structure ............................................ 206
2.2.51. TD_1_56 SR-IOV Extended Capability Structure ....................................................... 208
2.2.52. TD_1_57 MR-IOV Extended Capability Structure ..................................................... 214
2.2.53. TD_1_58 Secondary PCI Express Extended Capability Structure .............................. 216
2.2.54. TD_1_59 Protocol Multiplexing Extended Capability Structure ............................... 219
2.3. CONFIGURATION REGISTER TESTS (DEVICES WITH UPSTREAM PORTS) .................................. 225
2.3.1. TD_2_1 ASPM Configuration Stress (Upstream Ports) ............................................. 225
2.3.2. TD_2_2 Link Training Stress ..................................................................................... 226
2.3.3. TD_2_3 Tolerance of Hot-Plug Signaling/Ignored Messages ................................... 229
2.3.4. TD_2_4 Response To Earliest Allowed Configuration Requests After Reset ............ 230
2.3.5. TD_2_5 Response to Different Bus and Device Numbers ......................................... 232
2.3.6. TD_2_6 Secondary Bus Reset (Upstream Ports) ....................................................... 233
2.3.7. TD_2_7 Requested Link Speed (Upstream Ports) ..................................................... 234
2.3.8. TD_2_8 Supported Link Width (Upstream Ports) ..................................................... 238
2.3.9. TD_2_9 Software Requested Link Equalization (Upstream Ports) ........................... 240
2.4. CONFIGURATION REGISTER TESTS (DEVICES WITH DOWNSTREAM PORTS) ........................... 244
2.4.1. TD_3_1 Slot Capabilities, Slot Control, and Slot Status Registers
(PCIe Cap Ver = 1) ..................................................................................................... 244
2.4.2. TD_3_2 Root Capabilities, Root Control, and Root Status Registers
(PCIe Cap Ver = 1) ..................................................................................................... 249
2.4.3. TD_3_15 ASPM Configuration Stress (Downstream Ports) ...................................... 251
2.4.4. TD_3_13 Secondary Bus Reset (Downstream Ports) ................................................ 253
2.4.5. TD_3_10 Initiated Link Speed (Downstream Ports) .................................................. 254
PCI Express Architecture Configuration Space, Revision 3.0 5
2.4.6. TD_3_11 Supported Link Width (Downstream Ports) .............................................. 258
2.4.7. TD_3_12 ARI Downstream Ports Support non-Zero Device Number ........................ 261
2.4.8. TD_3_14 Software Initiated Link Equalization (Downstream Ports) ........................ 262
APPENDIX A. INFORMATIONAL TEST DETAILS .............................................. 266
A.1 TD_1_57X MR-IOV EXTENDED CAPABILITY STRUCTURE .......................................................... 266
APPENDIX B. OBSOLETE TEST DETAILS ......................................................... 347
B.1 TD_1_1 ...................................................................................................................................... 347
B.2 TD_1_33 ROOT COMPLEX INTEGRATED ENDPOINT ................................................................. 347
B.3 TD_1_35X CONFIGURATION ACCESS CORRELATION EXTENDED CAPABILITY STRUCTURE ...... 347
B.4 TD_1_36 TRUSTED CONFIG SPACE HEADER ............................................................................. 349
B.5 TD_1_37 CONFIGURATION ACCESS CORRELATION TRUSTED CAPABILITY STRUCTURE .......... 350
B.6 TD_1_38 VENDOR-SPECIFIC TRUSTED CAPABILITY STRUCTURE .............................................. 352
B.7 TD_3_3 ACCURATE SLOT REPORTING ...................................................................................... 354
B.8 TD_3_4 BASIC HOT-PLUG INSERTION ....................................................................................... 355
B.9 TD_3_5 BASIC HOT-PLUG REMOVAL ........................................................................................ 361
B.10 TD_3_6 BASIC HOT-PLUG SURPRISE REMOVAL ....................................................................... 365
B.11 TD_3_7 ATTENTION BUTTON MRL INDICATOR CONTROL ....................................................... 367
B.12 TD_3_8 LINK RETRAINING STRESS ............................................................................................ 374
B.13 TD_3_9 SLOT CAPABILITIES 2, SLOT CONTROL 2, AND SLOT STATUS 2 REGISTERS ................. 376
APPENDIX C. ACKNOWLEDGEMENTS ........................................................... 377
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