全志F1E200芯片手册

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Allwinner F1E200

Cost-Efficient E-Reader Processor up to 720P

Datasheet

Highlights

 Optimized ARM926-EJS 16KB

I-Cache/16KB D-Cache

 16 bits low cost SDR/DDR-I

 Support SLC/MLC NAND flash up to

64bits ECC

 Support SPI NOR flash

 H.264/MPEG1&2/MPEG4/Xvid

decoding up to 1280*720 @ 30fps

 Built in USB 2.0 HOST/OTG

 Built in MMC/SD/TF Card

 Built in Touch Panel Interface

 Built in LCD controller with PWM

 On-chip Sigma-Delta A/D with SNR up

to 95dB（A-Weight）

 On-chip Sigma-Delta D/A and PA with

SNR up to 100dB（A-Weight）

 Fully support PMU application

Package - eLQFP128 (16mm*16mm

)

AHB/APB Bus

UART TWI SD/MMC

Audio Codec

ARM926-

EJS

PIO

USB OTG

Video

Decoder

TPLRADCDE/TCON

Video

Encoder

JPEG

Decoder

TimerDMA PLL

PWM

USB HOST/OTG

OSD/TCON

MIC/Headphone

DMA

Touch PanelKEYCVBS

IRRX SD/MMC PIO PWM

Crystal

DDR

This document is supposed to be confidential. Neither institution nor individual is allowed to copy,

Table of Contents

1 DESCRIPTION......................................................................................................................... - 6 -

2 FEATURE.................................................................................................................................. - 6 -

3 SYSTEM BLOCK DIAGRAM................................................................................................ - 7 -

4 PIN ASSIGNMENT..................................................................................................................- 8 -

5 PIN DESCRIPTION.................................................................................................................- 8 -

5.1 SDR INTERFACE PIN.............................................................................................................- 8 -

5.2 NAND FLASH INTERFACE PIN..............................................................................................- 9 -

5.3 LCD INTERFACE PIN...........................................................................................................- 10 -

5.4 USB INTERFACE PIN...........................................................................................................- 11 -

5.5 TOUCH PANEL INTERFACE PIN ............................................................................................- 11 -

5.6 AUDIO CODEC INTERFACE PIN............................................................................................- 11 -

5.7 TV-OUT INTERFACE PIN .....................................................................................................- 12 -

5.8 CLOCK PIN..........................................................................................................................- 12 -

5.9 GENERAL PURPOSE IO PIN .................................................................................................- 12 -

5.10 MISCELLANEOUS SIGNAL PIN.............................................................................................- 12 -

5.11 POWER AND GROUND PIN...................................................................................................- 13 -

6 POWER DOMAIN.................................................................................................................. - 13 -

7 MODULE DESCRIPTION.................................................................................................... - 13 -

7.1 CLOCK CONTROL MODULE.................................................................................................- 13 -

7.1.1 CCM Overview............................................................................................................. - 13 -

7.1.2 CCM Diagram .............................................................................................................. - 15 -

7.2 INTERRUPT CONTROLLER ...................................................................................................- 16 -

7.2.1 Interrupt Overview ....................................................................................................... - 16 -

7.2.2 Interrupt Diagram ......................................................................................................... - 17 -

7.3 TIMER.................................................................................................................................- 17 -

7.3.1 Timer Overview............................................................................................................ - 17 -

7.3.2 Timer Diagram.............................................................................................................. - 18 -

7.4 PULSE WIDTH MODULATOR................................................................................................- 18 -

7.4.1 PWM Overview............................................................................................................ - 18 -

7.5 DMA..................................................................................................................................- 19 -

7.5.1 DMA Overview ............................................................................................................ - 19 -

7.6 SDRAM INTERFACE...........................................................................................................- 19 -

7.6.1 DRAM Controller Description ..................................................................................... - 19 -

7.7 NAND FLASH INTERFACE ..................................................................................................- 20 -

7.8 SD CARD INTERFACE..........................................................................................................- 21 -

7.8.1 SD Card Overview........................................................................................................ - 21 -

7.9 USB INTERFACE .................................................................................................................- 21 -

This document is supposed to be confidential. Neither institution nor individual is allowed to copy,

7.9.1 USB Overview.............................................................................................................. - 21 -

7.10 TWO WIRE INTERFACE........................................................................................................- 23 -

7.10.1 TWI Controller Description...................................................................................... - 23 -

7.10.2 TWI Controller Timing Diagram.............................................................................. - 23 -

7.11 SPI INTERFACE ...................................................................................................................- 24 -

7.11.1 SPI Description......................................................................................................... - 24 -

7.11.2 SPI Timing Diagram................................................................................................. - 24 -

7.12 UART INTERFACE ..............................................................................................................- 26 -

7.12.1 UART Overview....................................................................................................... - 26 -

7.12.2 UART Timing Diagram............................................................................................ - 27 -

7.13 IR INTERFACE.....................................................................................................................- 27 -

7.13.1 IR Overview ............................................................................................................. - 27 -

7.13.2 IR Timing Diagram................................................................................................... - 29 -

7.14 AUDIO CODEC ....................................................................................................................- 30 -

7.14.1 Description ............................................................................................................... - 30 -

7.14.2 Feature...................................................................................................................... - 30 -

7.14.3 Audio Codec Block Diagram ................................................................................... - 30 -

7.15 LRADC..............................................................................................................................- 31 -

7.15.1 Description ............................................................................................................... - 31 -

7.15.2 Feature...................................................................................................................... - 31 -

7.16 TOUCH PANEL.....................................................................................................................- 31 -

7.16.1 Description ............................................................................................................... - 31 -

7.17 GPIO INTERFACE................................................................................................................- 32 -

7.17.1 Port Description........................................................................................................ - 32 -

7.17.2 Port Configuration Table .......................................................................................... - 32 -

7.18 TV ENCODER......................................................................................................................- 34 -

7.18.1 Feature...................................................................................................................... - 34 -

7.18.2 Block diagram .......................................................................................................... - 35 -

7.19 UNIVERSAL LCD/TV TIMING CONTROLLER.......................................................................- 35 -

7.19.1 Feature...................................................................................................................... - 35 -

7.20 VIDEO DECODER ENGINE ...................................................................................................- 35 -

7.20.1 Video Decoder Engine Overview ............................................................................. - 35 -

8 PACKAGE SPECIFICATIONS............................................................................................. - 37 -

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