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更新于2023-03-16
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The MT8665 device (see ), with integrated Bluetooth, FM, WLAN and GPS modules, is a highly integrated baseband platform incorporating both modem and application processing subsystems to enable LTE smart platform applications,. The chip integrates Quad-core ARM® Cortex-A53operating up to 1.5GHz, an ARM® Cortex-R4 MCU and powerful multi-standard video codec. In addition, an extensive set of interfaces and connectivity peripherals are included to interface to cameras, touch-screen displays and MMC/SD cards.
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© 2016 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
M
Version: 1.2
Release date: 2016-03-24
Specifications are subject to change without notice.
MT8665 LTE SmartPlatform Application
Processor Technical Brief
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MT8665
LTE SmartPlatform Application Processor
Confidential A
MediaTek Confidential
© 2016 MediaTek Inc.
Page 2 of 85
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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Document Revision History
Revision
Date
Author
Description
1.0
2015-12-25
Junkai Yang
Initial draft
1.1
2015-12-26
Yuan Wen
Update HW diagram
1.2
2016-02-18
Junkai Yang
Update product information
MediaTek Confidential
MT8665
LTE SmartPlatform Application Processor
Confidential A
MediaTek Confidential
© 2016 MediaTek Inc.
Page 3 of 85
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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Table of Contents
Document Revision History...................................................................................................... 2
Table of Contents .................................................................................................................. 3
Preface ............................................................................................................................ 5
1 System Overview ..................................................................................................... 6
1.1 Highlighted Features Integrated in MT8665 .......................................................................... 6
1.2 Platform Features ..................................................................................................................... 8
1.3 MODEM Features ................................................................................................................... 10
1.4 Connectivity Features ............................................................................................................. 12
1.5 Multimedia Features ............................................................................................................... 14
1.6 General Description ................................................................................................................ 16
2 Product Description ...............................................................................................16
2.1 Pin Description ........................................................................................................................ 17
2.2 Electrical Characteristic .......................................................................................................... 53
2.3 System Configuration ............................................................................................................ 62
2.4 Power-on Sequence .................................................................................................................63
2.5 Analog Baseband .................................................................................................................... 64
2.6 Package Information .............................................................................................................. 84
2.7 Ordering Information ............................................................................................................ 85
Lists of Tables and Figures
Table 2-1. Pin coordinate (using LPDDR3) ................................................................................................ 18
Table 2-2 Acronym for pin type ................................................................................................................ 22
Table 2-3. Detailed pin description (using LPDDR3) .............................................................................. 23
Table 2-4. Acronym for the table of state of pins ...................................................................................... 32
Table 2-5. State of pins ............................................................................................................................... 33
Table 2-6. Acronym for pull-up and pull-down type ................................................................................ 37
Table 2-7. Pin multiplexing, capability and settings ................................................................................ 38
Table 2-8. Absolute maximum ratings for power supply ................................
......................................... 53
Table 2-9. Recommended operating conditions for power supply .......................................................... 53
Table 2-10. LPDDR3 AC timing parameter table of external memory interface .................................... 56
Table 2-11. LPDDR2 AC timing parameter table of external memory interface ..................................... 59
Table 2-12. Mode selection ......................................................................................................................... 62
MediaTek Confidential
MT8665
LTE SmartPlatform Application Processor
Confidential A
MediaTek Confidential
© 2016 MediaTek Inc.
Page 4 of 85
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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Table 2-13. Constant tied pins ................................................................................................................... 62
Table 2-14. Baseband downlink specifications ......................................................................................... 65
Table 2-15. Baseband downlink specifications ..........................................................................................67
Table 2-16. LTE_BBTX specifications ....................................................................................................... 68
Table 2-17. C2K_BBTX specifications ....................................................................................................... 70
Table 2-18. ETDAC specifications .............................................................................................................. 71
Table 2-19. APC-DAC specifications ........................................................................................................... 72
Table 2-20. Definitions of AUXADC channels ........................................................................................... 73
Table 2-21. AUXADC specifications ...........................................................................................................74
Table 2-22. Clock squarer specifications .................................................................................................... 75
Table 2-23. ARMPLL specifications ........................................................................................................... 77
Table 2-24. MAINPLL specifications
........................................................................................................ 78
Table 2-25. MMPLL specifications ............................................................................................................ 78
Table 2-26. UNIVPLL specifications ......................................................................................................... 78
Table 2-27. MSDCPLL specifications .........................................................................................................79
Table 2-28. WPLL specifications ................................................................................................................79
Table 2-29. WHPLL specifications .............................................................................................................79
Table 2-30. C2KCPPLL specifications ....................................................................................................... 80
Table 2-31. C2KDSPPLL specifications ..................................................................................................... 80
Table 2-32. CR4PLL specifications ............................................................................................................ 80
Table 2-33. VENCPLL specifications ......................................................................................................... 81
Table 2-34. TVDPLL specifications ............................................................................................................ 81
Table 2-35. LTEDSPPLL specifications ................................................................................................
...... 81
Table 2-36. APLL1 specifications ............................................................................................................... 82
Table 2-37. Temperature sensor specifications ........................................................................................ 82
Table 2-38. Thermal operating specifications .......................................................................................... 84
Figure 1-1. High-level MT8665 functional block diagram .......................................................................... 7
Figure 1-2. Block diagram of MT8665 Product Description ..................................................................... 16
Figure 2-1. Ball map view for LPDDR3 ...................................................................................................... 17
Figure 2-2. Ball map view for LPDDR2 ...................................................................................................... 18
Figure 2-3. IO types in state of pins ........................................................................................................... 37
Figure 2-4. Basic timing parameter for LPDDR3 commands ................................................................... 55
Figure 2-5. Basic timing parameter for LPDDR3 write ............................................................................. 55
Figure 2-6. Basic LPDDR3 read timing parameter .................................................................................. 56
Figure 2-7. Basic timing parameter for LPDDR2 commands .................................................................. 58
Figure 2-8. Basic timing parameter for LPDDR2 write ........................................................................... 59
Figure 2-9. Basic timing parameter for LPDDR2 read ............................................................................. 59
Figure 2-10. Block diagram of LTE_BBRX-ADC ...................................................................................... 65
Figure 2-11. Block diagram of C2K_BBRX-ADC .......................................................................................67
Figure 2-12. Block diagram of LTE_BBTX ............................................................................................... 68
Figure 2-13. Block diagram of C2K_BBTX ............................................................................................... 70
Figure 2-14. Block diagram of ETDAC ....................................................................................................... 71
Figure 2-15. Block diagram of APC-DAC (same architecture for two APC-DACs) .................................. 72
Figure 2-16. Block diagram of AUXADC .................................................................................................... 73
Figure 2-17. Block diagram of ARMPLL .....................................................................................................76
Figure
2-18. Block diagram of PLLGP ........................................................................................................ 77
Figure 2-19. Outlines and dimensions of VFBGA 12.6mm*12.6mm, 641 balls, 0.4mm pitch package 84
Figure 2-20. Top mark of MT8665 ............................................................................................................ 85
MediaTek Confidential
MT8665
LTE SmartPlatform Application Processor
Confidential A
MediaTek Confidential
© 2016 MediaTek Inc.
Page 5 of 85
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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Preface
Acronyms for register types
R/W
For both read and write access
RO
Read only
RC
Read only. After the register bank is read, every bit that is HIGH(1) will be cleared to
LOW(0) automatically.
WO
Write only
W1S
Write only. When data bits are written to the register bank, every bit that is HIGH(1) will
cause the corresponding bit to be set to 1. Data bits that are LOW(0) have no effects on the
corresponding bit.
W1C
Write only. When data bits are written to the register bank, every bit that is HIGH(1) will
cause the corresponding bit to be cleared to 0. Data bits that are LOW(0) have no effects on
the corresponding bit.
MediaTek Confidential
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