FPGA_ZynqUltraScale+MPSoC数据手册：概述_（Xilinx）.pdf_FPGA中文手册

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DS891 (v1.8) October 2, 2019 www.xilinx.com

Product Specification 1

trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, Arm1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks

of Arm in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and are used under license. All other trademarks are the property of their

respective owners.

General Description

The Zynq® UltraScale+™ MPSoC family is based on the Xilinx® UltraScale™ MPSoC architecture. This

family of products integrates a feature-rich 64-bit quad-core or dual-core Arm® Cortex™-A53 and

dual-core Arm Cortex-R5 based processing system (PS) and Xilinx programmable logic (PL) UltraScale

architecture in a single device. Also included are on-chip memory, multiport external memory interfaces,

and a rich set of peripheral connectivity interfaces.

Processing System (PS)

Arm Cortex-A53 Based Application

Processing Unit (APU)

• Quad-core or dual-core

• CPU frequency: Up to 1.5GHz

• Extendable cache coherency

• Armv8-A Architecture

o 64-bit or 32-bit operating modes

o TrustZone security

o A64 instruction set in 64-bit mode,

A32/T32 instruction set in 32-bit mode

• NEON Advanced SIMD media-processing engine

• Single/double precision Floating Point Unit (FPU)

• CoreSight™ and Embedded Trace Macrocell (ETM)

• Accelerator Coherency Port (ACP)

• AXI Coherency Extension (ACE)

• Power island gating for each processor core

• Timer and Interrupts

o Arm Generic timers support

o Two system level triple-timer counters

o One watchdog timer

o One global system timer

• Caches

o 32KB Level 1, 2-way set-associative

instruction cache with parity (independent for

each CPU)

o 32KB Level 1, 4-way set-associative data

cache with ECC (independent for each CPU)

o 1MB 16-way set-associative Level 2 cache

with ECC (shared between the CPUs)

Dual-core Arm Cortex-R5 Based

Real-Time Processing Unit (RPU)

• CPU frequency: Up to 600MHz

• Armv7-R Architecture

o A32/T32 instruction set

• Single/double precision Floating Point Unit (FPU)

• CoreSight™ and Embedded Trace Macrocell

(ETM)

• Lock-step or independent operation

• Timer and Interrupts:

o One watchdog timer

o Two triple-timer counters

• Caches and Tightly Coupled Memories (TCMs)

o 32KB Level 1, 4-way set-associative

instruction and data cache with ECC

(independent for each CPU)

o 128KB TCM with ECC (independent for each

CPU) that can be combined to become 256KB

in lockstep mode

On-Chip Memory

• 256KB on-chip RAM (OCM) in PS with ECC

• Up to 36Mb on-chip RAM (UltraRAM) with ECC in

• Up to 35Mb on-chip RAM (block RAM) with ECC

in PL

• Up to 11Mb on-chip RAM (distributed RAM) in PL

Zynq UltraScale+ MPSoC Data Sheet:

Overview

DS891 (v1.8) October 2, 2019

Product Specification

Zynq UltraScale+ MPSoC Data Sheet: Overview

DS891 (v1.8) October 2, 2019 www.xilinx.com

Product Specification 2

Arm Mali-400 Based GPU

• Supports OpenGL ES 1.1 and 2.0

• Supports OpenVG 1.1

• GPU frequency: Up to 667MHz

• Single Geometry Processor, Two Pixel Processors

• Pixel Fill Rate: 2 Mpixels/sec/MHz

• Triangle Rate: 0.11 Mtriangles/sec/MHz

• 64KB L2 Cache

• Power island gating

External Memory Interfaces

• Multi-protocol dynamic memory controller

• 32-bit or 64-bit interfaces to DDR4, DDR3,

DDR3L, or LPDDR3 memories, and 32-bit

interface to LPDDR4 memory

• ECC support in 64-bit and 32-bit modes

• Up to 32GB of address space using single or dual

rank of 8-, 16-, or 32-bit-wide memories

• Static memory interfaces

o eMMC4.51 Managed NAND flash support

o ONFI3.1 NAND flash with 24-bit ECC

o 1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or

two Quad-SPI (8-bit) serial NOR flash

8-Channel DMA Controller

• Two DMA controllers of 8-channels each

• Memory-to-memory, memory-to-peripheral,

peripheral-to-memory, and scatter-gather

transaction support

Serial Transceivers

• Four dedicated PS-GTR receivers and

transmitters supports up to 6.0Gb/s data rates

o Supports SGMII tri-speed Ethernet, PCI

Express® Gen2, Serial-ATA (SATA), USB3.0,

and DisplayPort

Dedicated I/O Peripherals and

Interfaces

• PCI Express — Compliant with PCIe® 2.1 base

specification

o Root complex and End Point configurations

o x1, x2, and x4 at Gen1 or Gen2 rates

• SATA Host

o 1.5, 3.0, and 6.0Gb/s data rates as defined by

SATA Specification, revision 3.1

o Supports up to two channels

• DisplayPort Controller

o Up to 5.4Gb/s rate

o Up to two TX lanes (no RX support)

• Four 10/100/1000 tri-speed Ethernet MAC

peripherals with IEEE Std 802.3 and IEEE Std 1588

revision 2.0 support

o Scatter-gather DMA capability

o Recognition of IEEE Std 1588 rev.2 PTP frames

o GMII, RGMII, and SGMII interfaces

o Jumbo frames

• Two USB 3.0/2.0 Device, Host, or OTG peripherals,

each supporting up to 12 endpoints

o USB 3.0/2.0 compliant device IP core

o Super-speed, high- speed, full-speed, and

low-speed modes

o Intel XHCI- compliant USB host

• Two full CAN 2.0B-compliant CAN bus interfaces

o CAN 2.0-A and CAN 2.0-B and ISO 118981-1

standard compliant

• Two SD/SDIO 2.0/eMMC4.51 compliant

controllers

• Two full-duplex SPI ports with three peripheral

chip selects

• Two high-speed UARTs (up to 1Mb/s)

• Two master and slave I2C interfaces

• Up to 78 flexible multiplexed I/O (MIO) (up to

three banks of 26 I/Os) for peripheral pin

assignment

• Up to 96 EMIOs (up to three banks of 32 I/Os)

connected to the PL

Interconnect

• High-bandwidth connectivity within PS

and between PS and PL

• Arm AMBA® AXI4-based

• QoS support for latency and bandwidth control

• Cache Coherent Interconnect (CCI)

System Memory Management

• System Memory Management Unit (SMMU)

• Xilinx Memory Protection Unit (XMPU)

Platform Management Unit

• Power gates PS peripherals, power islands, and

power domains

• Clock gates PS peripheral user firmware option

Configuration and Security Unit

• Boots PS and configures PL

• Supports secure and non-secure boot modes

System Monitor in PS

• On-chip voltage and temperature sensing

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