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Version 1.02.00 28-Jun-2010 MIPI Alliance Specification for DSI
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
MIPI Alliance Specification for
Display Serial Interface
Version 1.02.00 – 28 June 2010
MIPI Board Approved 20-Oct-2010
Further technical changes to this document are expected as work continues in the Display Working Group
Version 1.02.00 28-Jun-2010 MIPI Alliance Specification for DSI
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
ii
NOTICE OF DISCLAIMER 1
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled 2
by any of the authors or developers of this material or MIPI
®
. The material contained herein is provided on 3
an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS 4
AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all 5
other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if 6
any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of 7
accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of 8
negligence. 9
All materials contained herein are protected by copyright laws, and may not be reproduced, republished, 10
distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express 11
prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related 12
trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and 13
cannot be used without its express prior written permission. 14
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET 15
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD 16
TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY 17
AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR 18
MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE 19
GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, 20
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER 21
CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR 22
ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, 23
WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH 24
DAMAGES. 25
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is 26
further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the 27
contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; 28
and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance 29
with the contents of this Document. The use or implementation of the contents of this Document may 30
involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents, 31
patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI 32
does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any 33
IPR or claims of IPR as respects the contents of this Document or otherwise. 34
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 35
MIPI Alliance, Inc. 36
c/o IEEE-ISTO 37
445 Hoes Lane 38
Piscataway, NJ 08854 39
Attn: Board Secretary 40
41
Version 1.02.00 28-Jun-2010 MIPI Alliance Specification for DSI
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
iii
Contents 42
Version 1.02.00 – 28 June
2010 ....................................................................................................................... i43
1
Overview ............................................................................................................................................... 1044
1.1
Scope ............................................................................................................................................. 1045
1.2
Purpose .......................................................................................................................................... 1046
2
Terminology (informative) .................................................................................................................... 1147
2.1
Definitions ..................................................................................................................................... 1148
2.2
Abbreviations ................................................................................................................................ 1249
2.3
Acronyms ...................................................................................................................................... 1250
3
References (informative) ....................................................................................................................... 1551
3.1
Display Bus Interface Standard for Parallel Signaling (DBI-2) .................................................... 1552
3.2
Display Pixel Interface Standard for Parallel Signaling (DPI-2) ................................................... 1653
3.3
MIPI Alliance Specification for Display Command Set (DCS) .................................................... 1654
3.4
MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2)..................................................... 1655
3.5
MIPI Alliance Specification for D-PHY (D-PHY) ........................................................................ 1656
4
DSI Introduction .................................................................................................................................... 1757
4.1
DSI Layer Definitions ................................................................................................................... 1858
4.2
Command and Video Modes ......................................................................................................... 1959
4.2.1
Command Mode .................................................................................................................... 1960
4.2.2
Video Mode Operation .......................................................................................................... 1961
4.2.3
Virtual Channel Capability .................................................................................................... 2062
5
DSI Physical Layer ................................................................................................................................ 2163
5.1
Data Flow Control ......................................................................................................................... 2164
5.2
Bidirectionality and Low Power Signaling Policy ........................................................................ 2165
5.3
Command Mode Interfaces ........................................................................................................... 2266
5.4
Video Mode Interfaces .................................................................................................................. 2267
5.5
Bidirectional Control Mechanism ................................................................................................. 2268
5.6
Clock Management ........................................................................................................................ 2369
5.6.1
Clock Requirements .............................................................................................................. 2370
5.6.2
Clock Power and Timing ....................................................................................................... 2471
5.7
System Power-Up and Initialization .............................................................................................. 2472
6
Multi-Lane Distribution and Merging ................................................................................................... 2673
6.1
Multi-Lane Interoperability and Lane-number Mismatch ............................................................. 2774
6.1.1
Clock Considerations with Multi-Lane .................................................................................. 2875
6.1.2
Bidirectionality and Multi-Lane Capability ........................................................................... 2876
6.1.3
SoT and EoT in Multi-Lane Configurations .......................................................................... 2877
Version 1.02.00 28-Jun-2010 MIPI Alliance Specification for DSI
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
iv
7
Low-Level Protocol Errors and Contention .......................................................................................... 3178
7.1
Low-Level Protocol Errors ............................................................................................................ 3179
7.1.1
SoT Error ............................................................................................................................... 3180
7.1.2
SoT Sync Error ...................................................................................................................... 3281
7.1.3
EoT Sync Error ...................................................................................................................... 3282
7.1.4
Escape Mode Entry Command Error ..................................................................................... 3383
7.1.5
LP Transmission Sync Error .................................................................................................. 3384
7.1.6
False Control Error ................................................................................................................ 3385
7.2
Contention Detection and Recovery .............................................................................................. 3486
7.2.1
Contention Detection in LP Mode ......................................................................................... 3487
7.2.2
Contention Recovery Using Timers ...................................................................................... 3488
7.3
Additional Timers .......................................................................................................................... 3789
7.3.1
Turnaround Acknowledge Timeout (TA_TO) ....................................................................... 3790
7.3.2
Peripheral Reset Timeout (PR_TO) ....................................................................................... 3791
7.4
Acknowledge and Error Reporting Mechanism ............................................................................ 3892
8
DSI Protocol .......................................................................................................................................... 3993
8.1
Multiple Packets per Transmission ................................................................................................ 3994
8.2
Packet Composition ....................................................................................................................... 4095
8.3
Endian Policy ................................................................................................................................ 4196
8.4
General Packet Structure ............................................................................................................... 4197
8.4.1
Long Packet Format ............................................................................................................... 4198
8.4.2
Short Packet Format .............................................................................................................. 4399
8.5
Common Packet Elements ............................................................................................................. 43100
8.5.1
Data Identifier Byte ............................................................................................................... 43101
8.5.2
Error Correction Code ........................................................................................................... 44102
8.6
Interleaved Data Streams ............................................................................................................... 45103
8.6.1
Interleaved Data Streams and Bidirectionality ...................................................................... 45104
8.7
Processor to Peripheral Direction (Processor-Sourced) Packet Data Types .................................. 46105
8.8
Processor-to-Peripheral Transactions – Detailed Format Description ........................................... 47106
8.8.1
Sync Event (H Start, H End, V Start, V End), Data Type = XX 0001 (0xX1) ...................... 47107
8.8.2
EoTp, Data Type = 00 1000 (0x08) ....................................................................................... 47108
8.8.3
Color Mode Off Command, Data Type = 00 0010 (0x02) .................................................... 48109
8.8.4
Color Mode On Command, Data Type = 01 0010 (0x12) ..................................................... 48110
8.8.5
Shutdown Peripheral Command, Data Type = 10 0010 (0x22) ............................................. 49111
8.8.6
Turn On Peripheral Command, Data Type = 11 0010 (0x32) ............................................... 49112
8.8.7
Generic Short WRITE Packet with 0, 1, or 2 parameters, Data Types = 00 0011 (0x03), 01 113
0011 (0x13), 10 0011 (0x23), Respectively .......................................................................................... 49
114
Version 1.02.00 28-Jun-2010 MIPI Alliance Specification for DSI
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
v
8.8.8
Generic READ Request with 0, 1, or 2 Parameters, Data Types = 00 0100 (0x04), 01 0100 115
(0x14), 10 0100(0x24), Respectively .................................................................................................... 49
116
8.8.9
DCS Commands .................................................................................................................... 50117
8.8.10
Set Maximum Return Packet Size, Data Type = 11 0111 (0x37) .......................................... 51118
8.8.11
Null Packet (Long), Data Type = 00 1001 (0x09) ................................................................. 51119
8.8.12
Blanking Packet (Long), Data Type = 01 1001 (0x19) .......................................................... 51120
8.8.13
Generic Long Write, Data Type = 10 1001 (0x29) ................................................................ 51121
8.8.14
Loosely Packed Pixel Stream, 20-bit YCbCr 4:2:2 Format, Data Type = 00 1100 (0x0C) ... 51122
8.8.15
Packed Pixel Stream, 24-bit YCbCr 4:2:2 Format, Data Type = 01 1100 (0x1C) ................. 53123
8.8.16
Packed Pixel Stream, 16-bit YCbCr 4:2:2 Format, Data Type = 10 1100 (0x2C) ................. 54124
8.8.17
Packed Pixel Stream, 30-bit Format, Long Packet, Data Type = 00 1101 (0x0D) ................ 54125
8.8.18
Packed Pixel Stream, 36-bit Format, Long Packet, Data Type = 01 1101 (0x1D) ................ 55126
8.8.19
Packed Pixel Stream, 12-bit YCbCr 4:2:0 Format, Data Type = 11 1101 (0x3D) ................ 56127
8.8.20
Packed Pixel Stream, 16-bit Format, Long Packet, Data Type 00 1110 (0x0E) .................... 57128
8.8.21
Packed Pixel Stream, 18-bit Format, Long Packet, Data Type = 01 1110 (0x1E) ................. 58129
8.8.22
Pixel Stream, 18-bit Format in Three Bytes, Long Packet, Data Type = 10 1110 (0x2E) ..... 60130
8.8.23
Packed Pixel Stream, 24-bit Format, Long Packet, Data Type = 11 1110 (0x3E) ................. 61131
8.8.24
DO NOT USE and Reserved Data Types .............................................................................. 62132
8.9
Peripheral-to-Processor (Reverse Direction) LP Transmissions ................................................... 62133
8.9.1
Packet Structure for Peripheral-to-Processor LP Transmissions ........................................... 62134
8.9.2
System Requirements for ECC and Checksum and Packet Format ....................................... 63135
8.9.3
Appropriate Responses to Commands and ACK Requests.................................................... 63136
8.9.4
Format of Acknowledge and Error Report and Read Response Data Types ......................... 65137
8.9.5
Error Reporting Format ......................................................................................................... 65138
8.10
Peripheral-to-Processor Transactions – Detailed Format Description ........................................... 67139
8.10.1
Acknowledge and Error Report, Data Type 00 0010 (0x02) ................................................. 68140
8.10.2
Generic Short Read Response, 1 or 2 Bytes, Data Types = 01 0001 or 01 0010, Respectively141
68
142
8.10.3
Generic Long Read Response with Optional Checksum, Data Type = 01 1010 (0x1A) ....... 68143
8.10.4
DCS Long Read Response with Optional Checksum, Data Type 01 1100 (0x1C) ............... 69144
8.10.5
DCS Short Read Response, 1 or 2 Bytes, Data Types = 10 0001 or 10 0010, Respectively . 69145
8.10.6
Multiple Transmissions and Error Reporting ........................................................................ 69146
8.10.7
Clearing Error Bits ................................................................................................................. 69147
8.11
Video Mode Interface Timing ....................................................................................................... 69148
8.11.1
Transmission Packet Sequences ............................................................................................ 70149
8.11.2
Non-Burst Mode with Sync Pulses ........................................................................................ 71150
8.11.3
Non-Burst Mode with Sync Events ....................................................................................... 72151
8.11.4
Burst Mode ............................................................................................................................ 73152
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