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Zynq UltraScale+ Device
Packaging and Pinouts
Product Specification User Guide
UG1075 (v1.6) August 20, 2018
Zynq UltraScale+ Packaging and Pinouts 2
UG1075 (v1.6) August 20, 2018 www.xilinx.com
Revision History
The following table shows the revision history for this document.
Date Version Revision
8/20/2018 1.6 Chapter 1: Added the XAZU4EV and XAZU5EV devices in the SFVC784 package. This
includes updates to Table 1-2, Table 1-3, Table 1-5, Table 1-6, Table 1-7, Figure 1-6,
and Figure 1-7. Corrected the VCCO_PSDDR pin name (from VCCO_PSDDR_504) in
Table 1-4. Added a note to Figure 1-3 on page 38.
Chapter 2: Clarified what a byte lane includes in the pin swapping restrictions
discussions on page 72 and page 76.
Chapter 3: Added the XAZU4EV and XAZU5EV devices to Table 3-1. Labeled all of the
devices in Table 3-2 as production.
Chapter 4: In Table 4-1, added the XAZU4EV and XAZU5EV devices and changed the
XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR device labels to
production. Added a note above Figure 4-1 on page 96. Added the XAZU4EV and
XAZU5EV devices in the SFVC784 package to Figure 4-9 and Figure 4-10.
Chapter 5: Added the XAZU4EV and XAZU5EV devices to Table 5-1 and Figure 5-3.
Labeled all of the devices in Table 5-2 as production.
Chapter 10: Added the XAZU4EV and XAZU5EV devices to Table 10-1.
4/10/2018 1.5 Chapter 1: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR
devices. This includes updates to Table 1-1, Table 1-2, Table 1-3, Table 1-4, Table 1-5,
Table 1-6, and Table 1-7. Added Figure 1-30 through Figure 1-41.
Chapter 3: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR
ASCII file links, see Table 3-2.
Chapter 4: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR
devices to Table 4-1.
Chapter 5: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR
mechanical drawings, see Table 5-2.
Chapter 7: Added the FFVD1156, FFVE1156, FSVE1156, FFVG1517, FSVG1517,
FFVF1760, and FSVF1760 packages to Table 7-1.
Chapter 8: Revised the guidelines in Table 8-1 for Ramp-up rate, Peak temperature
(lead/ball), and Peak temperature (body). Revised the same information in Figure 8-1.
Added the FFVD1156, FFVE1156, FSVE1156, FFVG1517, FSVG1517, FFVF1760, and
FSVF1760 packages to Table 8-2.
Chapter 10: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and
XCZU29DR devices to Table 10-1 and added Note 1.
Chapter 11: Updated the System Level Heat Sink Solutions section and added the
Heat Sink Removal and Measurement Debug sections.
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Zynq UltraScale+ Packaging and Pinouts 3
UG1075 (v1.6) August 20, 2018 www.xilinx.com
12/21/2017 1.4 Added the XAZU2EG and XAZU3EG devices throughout the document.
Chapter 1: Revise the VCCINT_VCU description in Table 1-4. Updated the ZU11EG
(Figure 1-16 through Figure 1-20) PCIE4 bank coordinates.
Chapter 2: Updated LPDDR4 Pin Swapping Restrictions and DDR4 Pin Swapping
Restrictions and removed Figure 2-1: DDR Controller Implementation of DQ
Mapping. In Table 2-2, updated the PS_DDR_ZQ connections.
Chapter 5: Revised Figure 5-4: Symbol A from (2.57/2.77/2.97) to (2.48/2.68/2.88) and
Symbol A2 from (1.27/1.42/1.62) to (1.18/1.33/1.48).
Chapter 6: Revised the top mark diagram to show both older device versions and
newer ones with a 2D bar code.
Chapter 8: Added an Important note on page 177 about reflow rework.
Chapter 10: Updated the SFVC784, FFVC900, FFVB1156, FFVC1156, FFVB1517,
FFVF1517 data to account for the stamped lid in Table 10-1.
8/29/2017 1.3 In Chapter 1, updated Figure 1-3, Figure 1-13, Figure 1-14, Figure 1-15, Figure 1-21,
Figure 1-22, Figure 1-23, Figure 1-24, Figure 1-25, Figure 1-26, Figure 1-27, and
Figure 1-28. Revise the VCCINT_VCU description in Table 1-4.
In Chapter 2, updated the DDR4 Pin Rules and the DDR4 Pin Swapping Restrictions.
In Table 2-2, updated the configurations for PS_DDR_CK_N1 (DDR4 1Rank).
In Chapter 3, updated the package specification designation of many of the packages
listed in Table 3-1.
In Chapter 4, updated Table 4-1 and added the following device diagrams:
SFVC784
Package–XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG, SFVC784 Package–XCZU4EV,
XCZU5EV, XAZU4EV, and XAZU5EV, FBVB900 Package–XCZU4CG, XCZU4EG, XCZU5CG,
and XCZU5EG, FBVB900 Package–XCZU4EV and XCZU5EV, FFVF1517 Package–
XCZU7CG and XCZU7EG, FFVC1156 Package–XCZU7EV, FFVC1156 Package–
XCZU11EG, FFVB1517 Package–XCZU11EG, FFVF1517 Package–XCZU11EG, and
FFVC1760 Package–XCZU11EG.
In Chapter 5, replace Figure 5-3, added Figure 5-4, Figure 5-5, Figure 5-11, and
Figure 5-17.
In Table 8-2, update the FFV packages to a mass reflow of 245°C.
1/13/2017 1.2 Added the following devices throughout: XCZU2CG, XCZU3CG, XCZU4CG, XCZU4EG,
XCZU5CG, XCZU5EG, XCZU6CG, XCZU7CG, XCZU7EG, and XCZU9CG. In Table 1-3,
revised the available PS I/O pin values for the SBVA484 and SFVA625 packages. In
Table 1-4, updated the PS_MODE directions and the pin descriptions in the
Power/Ground Pins section. In Table 1-6, revised the XCZU4 bank numbers and
updated the FBVB900 mapping. Revised the mapping for the FBVB900 package in
Table 1-7. Revised the Bank Locations of Dedicated and Multi-Function Pins section.
Updated the HD I/O bank numbers in Figure 1-20.
Added Chapter 2, PS Memory Interface Pin Guidelines. Added the Chapter 3, Package
Specifications Designations section. In Table 3-1, updated links. Chapter 4, Device
Diagrams and Chapter 5, Mechanical Drawings have updated tables and new
diagrams. Revised the Bar Code section of Table 6-1 to include changes outlined in
XCN16014: Top Marking change for 7 Series, UltraScale, and UltraScale+ Products.
Updated the AUTOMOTIVE APPLICATIONS DISCLAIMER.
Date Version Revision
Send Feedback
Zynq UltraScale+ Packaging and Pinouts 4
UG1075 (v1.6) August 20, 2018 www.xilinx.com
6/14/2016 1.1 In Table 1-3, updated Note 1 and the SBVA484 package total user HP I/Os. Clarified
the I2C_SCLK and I2C_SDA descriptions and added SMBALERT and VCCINT_VCU to
Table 1-4. Also updated the Multi-gigabit Serial Transceiver Pins (GTHE4, GTYE4, and
PS-GTR) descriptions, Added further descriptions in the Die Level Bank Numbering
Overview including adding an example device diagram (Figure 1-1). In Chapter 4,
added new figures and updated all of the graphics because the PERSTN pins and
SMBALERT pins have moved. Updated Figure 5-7 and added Figure 5-8. Added the
bar code description in Chapter 6.
1/20/2016 1.0.2 Replaced the missing graphics in Chapter 1.
12/18/2015 1.0.1 Updated the package file links in Chapter 3.
11/24/2015 1.0 Initial Xilinx release.
Date Version Revision
Send Feedback
Zynq UltraScale+ Packaging and Pinouts 5
UG1075 (v1.6) August 20, 2018 www.xilinx.com
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Packaging Overview
Introduction to the UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Zynq UltraScale+ Device Packaging and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Differences from Previous Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device/Package Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Gigabit Transceiver Channels by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
User I/O Pins by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Footprint Compatibility between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 2: PS Memory Interface Pin Guidelines
Introduction to PS Memory Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DDR3/3L Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DDR4 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LPDDR4 Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LPDDR3 Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 3: Package Files
About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Package Specifications Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Chapter 4: Device Diagrams
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SBVA484 Package–XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . . 96
SFVA625 Package–XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . . 98
SFVC784 Package–XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . 100
SFVC784 Package–XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG . . . . . . . . . . . . . . . . . . . . . . . . . 102
SFVC784 Package–XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV . . . . . . . . . . . . . . . . . . . . . . . . . 104
FBVB900 Package–XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG . . . . . . . . . . . . . . . . . . . . . . . . . 106
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