S32K1xxMCUFamilyReferenceManual（英文手册）_S32K1xxMCUFamily-ReferenceManual

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S32K1xx Series Reference Manual

Supports S32K116, S32K118, S32K142, S32K144, S32K146, and

S32K148

Document Number: S32K1XXRM

Rev. 9, 09/2018

Contents

Section number Title Page

Chapter 1

About This Manual

1.1 Audience....................................................................................................................................................................... 49

1.2 Organization..................................................................................................................................................................49

1.3 Module descriptions......................................................................................................................................................49

1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 50

1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 51

1.4 Register descriptions.....................................................................................................................................................52

1.5 Conventions.................................................................................................................................................................. 53

1.5.1 Notes, Cautions, and Warnings......................................................................................................................53

1.5.2 Numbering systems........................................................................................................................................53

1.5.3 Typographic notation..................................................................................................................................... 54

1.5.4 Special terms..................................................................................................................................................54

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................57

2.2 S32K1xx Series introduction........................................................................................................................................57

2.2.1 S32K14x.........................................................................................................................................................57

2.2.2 S32K11x ........................................................................................................................................................59

2.3 Feature summary...........................................................................................................................................................60

2.4 Block diagram...............................................................................................................................................................63

2.5 Feature comparison.......................................................................................................................................................64

2.5.1 Differences between S32K14x and S32K11x................................................................................................66

2.6 Applications..................................................................................................................................................................67

2.7 Module functional categories........................................................................................................................................68

2.7.1 Arm Cortex-M4F Core Modules....................................................................................................................69

2.7.2 Arm Cortex-M0+ Core Modules....................................................................................................................70

2.7.3 System modules............................................................................................................................................. 70

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Section number Title Page

2.7.4 Memories and memory interfaces..................................................................................................................71

2.7.5 Power Management........................................................................................................................................72

2.7.6 Clocking.........................................................................................................................................................72

2.7.7 Analog modules............................................................................................................................................. 73

2.7.8 Timer modules............................................................................................................................................... 73

2.7.9 Communication interfaces............................................................................................................................. 74

2.7.10 Debug modules.............................................................................................................................................. 75

Chapter 3

Memory Map

3.1 Introduction...................................................................................................................................................................77

3.2 SRAM memory map.....................................................................................................................................................77

3.2.1 S32K14x: SRAM memory map ....................................................................................................................77

3.2.2 S32K11x: SRAM memory map ....................................................................................................................77

3.3 Flash memory map........................................................................................................................................................78

3.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................78

3.4.1 Read-after-write sequence and required serialization of memory operations................................................79

3.5 Private Peripheral Bus (PPB) memory map..................................................................................................................80

3.6 Aliased bit-band regions for CM4 core........................................................................................................................ 81

Chapter 4

Signal Multiplexing and Pin Assignment

4.1 Introduction...................................................................................................................................................................83

4.2 Functional description...................................................................................................................................................83

4.3 Pad description..............................................................................................................................................................84

4.4 Default pad state........................................................................................................................................................... 85

4.5 Signal Multiplexing sheet............................................................................................................................................. 86

4.5.1 IO Signal Table ............................................................................................................................................. 86

4.5.2 Input muxing table......................................................................................................................................... 88

4.6 Pinout diagrams............................................................................................................................................................ 89

Chapter 5

Security Overview

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Section number Title Page

5.1 Introduction...................................................................................................................................................................91

5.2 Device security..............................................................................................................................................................91

5.2.1 Flash memory security...................................................................................................................................91

5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................92

5.2.3 Device Boot modes........................................................................................................................................ 93

5.3 Security use case examples...........................................................................................................................................93

5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 93

5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 94

5.3.3 Secure communication...................................................................................................................................95

5.3.4 Component protection....................................................................................................................................96

5.3.5 Message-authentication example................................................................................................................... 97

5.4 Steps required before failure analysis...........................................................................................................................98

5.5 Security programming flow example (Secure Boot).................................................................................................... 99

Chapter 6

Safety Overview

6.1 Introduction...................................................................................................................................................................101

6.2 S32K1xx safety concept............................................................................................................................................... 102

6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST).......................................................................................103

6.2.2 ECC on RAM and flash memory...................................................................................................................104

6.2.3 Power supply monitoring...............................................................................................................................104

6.2.4 Clock monitoring........................................................................................................................................... 105

6.2.5 Temporal protection.......................................................................................................................................105

6.2.6 Operational interference protection............................................................................................................... 105

6.2.7 CRC................................................................................................................................................................107

6.2.8 Diversity of system resources........................................................................................................................ 107

Chapter 7

CM4 Overview

7.1 Arm Cortex-M4F core configuration............................................................................................................................109

7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 110

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