RTL8380M_RTL8382M_RTL8382L_Datasheet_Draft_v0.10.pdf

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RTL8380M-CG

MULTI-LAYER MANAGED 10*10/100/1000M-PORT SWITCH CONTROLLERS

RTL8382M-CG

MULTI-LAYER MANAGED 28*10/100/1000M-PORT SWITCH CONTROLLERS

RTL8382L-CG

UN-MANAGED 26*10/100/1000M-PORT SWITCH CONTROLLERS

DRAFT DATASHEET

(CONFIDENTIAL: Development Partners Only)

Rev. 0.10

20 June. 2013

Track ID:

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211 Fax: +886-3-577-6047

www.realtek.com

RTL8380M/RTL8382M/RTL8382L

Datasheet

10-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers ii Track ID: Rev. 0.10

transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements

and/or changes in this document or in the product described in this document at any time. This document

could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document

are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document provides detailed user guidelines to achieve the best performance when implementing the

Realtek Ethernet Switch Controllers.

Though every effort has been made to ensure that this document is current and accurate, more information

may have become available subsequent to the production of this guide.

REVISION HISTORY

Revision Release Date Summary

0.1 2012/05/12 Initial draft.

0.2 2012/08/08 Updated.

0.3 2012/09/18 Revised the pin description error for MEM_TYPE[1:0] on table 14, 30 and 44.

0.4 2012/10/18

Add 11.4 AC characteristics；

0.5 2013/01/24

Update RTL8382L pin assignment；

Add uart1 interface description;

Add GPIO[14:11] and GPO10 description;

Modify the ddr2 and spi flash timing Characteristics；

Add ddr3 timing Characteristics；

0.6 2013/02/20 Modify the description for CLK_M_EE[1:0];

0.7 2013/05/02 Modify the AC Characteristic of QSGMII VTX-DIFFp-p and VRX-DIFFp-p;

Modify the operating range of the DVDDL, AVDDL, SVDDL, AVDDL_PLL,

PLLVDDL and VDDIO.

0.8 2013/05/17 Modify the application of RTL8380M from 16G+2FX to 8G+2FX.

0.9 2013/06/17 Add AC Characteristic for 1000Base-X/100Base-FX

0.10 2013/06/20

Add serial mode led timing characteristics；

RTL8380M/RTL8382M/RTL8382L

Datasheet

10-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers iii Track ID: Rev. 0.10

Table of Contents

1. GENERAL DESCRIPTION..............................................................................................................................................1

2. FEATURES.........................................................................................................................................................................3

3. SYSTEM APPLICATIONS...............................................................................................................................................4

3.1. RTL8380M: MANAGED 8*1000M UTP+2*1000BASE-X SWITCH ..............................................................................4

3.2. RTL8382M: MANAGED 28*1000M SWITCH VIA RTL8218B PHY .............................................................................5

3.3. RTL8382M: MANAGED 20*1000M UTP+4*1000M COMBO SWITCH ........................................................................6

3.4. RTL8382M/RTL8382L: MANAGED/UNMANAGED 24*1000M UTP+2*1000BASE-X SWITCH ..................................7

4. BLOCK DIAGRAMS.........................................................................................................................................................8

4.1. RTL8380M BLOCK DIAGRAM .....................................................................................................................................8

4.2. RTL8382M BLOCK DIAGRAM .....................................................................................................................................9

4.3. RTL8382L BLOCK DIAGRAM ....................................................................................................................................10

5. PIN ASSIGNMENTS AND DESCRIPTION (RTL8380M)..........................................................................................11

5.1. PIN ASSIGNMENTS FIGURE (RTL8380M) ..................................................................................................................11

5.2. PACKAGE IDENTIFICATION.........................................................................................................................................12

5.3. PIN ASSIGNMENTS TABLE CODES (RTL8380M)........................................................................................................12

5.4. PIN ASSIGNMENTS TABLE (RTL8380M)....................................................................................................................12

5.5. PIN DESCRIPTIONS (RTL8380M)...............................................................................................................................16

5.5.1. 1000M Ethernet PHY MDI Interface Pins............................................................................................................16

5.5.2. SGMII Interface Pins............................................................................................................................................17

5.5.3. RSGMII Interface Pins.........................................................................................................................................18

5.5.4. 1000Base-X/100Base-FX Interface Pins..............................................................................................................18

5.5.5. DDR1/2 SDRAM Interface Pins ...........................................................................................................................18

5.5.6. DDR3 SDRAM Interface Pins ..............................................................................................................................19

5.5.7. Master Mode-SPI Flash Interface Pins................................................................................................................20

5.5.8. UART Interface Pins.............................................................................................................................................20

5.5.9. LED Interface Pins...............................................................................................................................................20

5.5.10. GPIO Interface Pins........................................................................................................................................21

5.5.11. EJTAG Interface Pins......................................................................................................................................21

5.5.12. Configuration Strapping Pins..........................................................................................................................21

5.5.13. Miscellaneous Interface Pins...........................................................................................................................22

5.5.14. Power and GND Pins ......................................................................................................................................23

6. PIN ASSIGNMENTS AND DESCRIPTION (RTL8382M)..........................................................................................24

6.1. PIN ASSIGNMENTS FIGURE (RTL8382M) ..................................................................................................................24

6.2. PACKAGE IDENTIFICATION.........................................................................................................................................25

6.3. PIN ASSIGNMENTS TABLE CODES (RTL8382M)........................................................................................................25

6.4. PIN ASSIGNMENTS TABLE (RTL8382M)....................................................................................................................25

6.5. PIN DESCRIPTION (RTL8382M).................................................................................................................................30

6.5.1. 1000M Ethernet PHY MDI Interface Pins............................................................................................................30

6.5.2. SGMII Interface Pins............................................................................................................................................32

6.5.3. RSGMII Interface Pins.........................................................................................................................................32

6.5.4. QSGMII Interface Pins.........................................................................................................................................32

6.5.5. 1000Base-X/100Base-FX Interface Pins..............................................................................................................33

6.5.6. DDR1/2 SDRAM Interface Pins ...........................................................................................................................33

6.5.7. DDR3 SDRAM Interface Pins ..............................................................................................................................34

6.5.8. Master Mode-SPI Flash Interface Pins................................................................................................................35

6.5.9. UART Interface Pins.............................................................................................................................................35

6.5.10. LED Interface Pins..........................................................................................................................................35

6.5.11. GPIO Interface Pins........................................................................................................................................35

RTL8380M/RTL8382M/RTL8382L 
Datasheet 
10-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers  iv  Track ID:    Rev. 0.10
 
 
5.12.  EJTAG Interface Pins......................................................................................................................................36 
5.13.  Configuration Strapping Pins..........................................................................................................................36 
5.14.  Miscellaneous Interface Pins...........................................................................................................................37 
5.15.  Power and GND Pins ......................................................................................................................................38 
 PIN ASSIGNMENTS AND DESCRIPTION (RTL8382L)...........................................................................................39 
1.  PIN ASSIGNMENTS FIGURE (RTL8382L) ...................................................................................................................39 
2.  PACKAGE IDENTIFICATION.........................................................................................................................................40 
3.  PIN ASSIGNMENTS TABLE CODES (RTL8382L).........................................................................................................40 
4.  PIN ASSIGNMENTS TABLE (RTL8382L).....................................................................................................................40 
5.  PIN DESCRIPTIONS (RTL8382L) ................................................................................................................................44 
5.1.  1000M Ethernet PHY MDI Interface Pins............................................................................................................44 
5.2.  SGMII Interface Pins............................................................................................................................................46 
5.3.  QSGMII Interface Pins.........................................................................................................................................46 
5.4.  1000Base-X/100Base-FX Interface Pins..............................................................................................................46 
5.5.  Master Mode-SPI Flash Interface Pins................................................................................................................47 
5.6.  UART Interface Pins.............................................................................................................................................47 
5.7.  LED Interface Pins...............................................................................................................................................47 
5.8.  GPIO Interface Pins.............................................................................................................................................48 
5.9.  Configuration Strapping Pins...............................................................................................................................48 
5.10.  Miscellaneous Interface Pins...........................................................................................................................49 
5.11.  Power and GND Pins ......................................................................................................................................50 
 SWITCH FUNCTION DESCRIPTION.........................................................................................................................51 
1.  HARDWARE RESET AND SOFTWARE RESET................................................................................................................51 
1.1.  Hardware Reset....................................................................................................................................................51 
1.2.  Software Reset......................................................................................................................................................51 
2.  CRYSTAL....................................................................................................................................................................51 
3.  IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) ................................................................................................51 
4.  LAYER 2 LEARNING AND FORWARDING .....................................................................................................................52 
4.1.  Forwarding...........................................................................................................................................................52 
4.2.  Learning ...............................................................................................................................................................52 
4.3.  DA/SA Block.........................................................................................................................................................52 
5.  PORT ISOLATION ........................................................................................................................................................53 
6.  IEEE 802.3X FLOW CONTROL ...................................................................................................................................54 
7.  HALF DUPLEX BACKPRESSURE ..................................................................................................................................55 
7.1.  Collision-Based Backpressure (Jam Mode) .........................................................................................................55 
7.2.  Carrier-Based Backpressure (I.e., Defer Mode) ..................................................................................................55 
8.  LAYER 2 MULTICAST AND IP MULTICAST .................................................................................................................56 
9.  IEEE 802.1D/1W/1S (STP/RSTP/MSTP)...................................................................................................................56 
10.  IEEE 802.1P AND IEEE 802.1Q (VLAN) ..................................................................................................................57 
11.  IEEE 802.1X (NETWORK ACCESS CONTROL)............................................................................................................58 
12.  RESERVED MULTICAST ADDRESS HANDLING ............................................................................................................59 
13.  LAYER 2 TRAFFIC SUPPRESSION (STORM CONTROL) .................................................................................................60 
14.  PIE (PACKET INSPECTION ENGINE)............................................................................................................................60 
14.1.  Ingress ACL.....................................................................................................................................................60 
15.  INPUT BANDWIDTH CONTROL AND ACL TRAFFIC METER.........................................................................................61 
15.1.  Input Bandwidth Control.................................................................................................................................61 
15.2.  ACL Traffic Meter............................................................................................................................................61 
16.  IEEE 802.3AD LINK AGGREGATION PROTOCOL ........................................................................................................61 
17.  IEEE 802.1AD VLAN STACKING...............................................................................................................................62 
18.  QUALITY OF SERVICE (QOS)......................................................................................................................................63 
19.  PACKET SCHEDULING (WRR AND WFQ)...................................................................................................................64 
20.  PACKET DROP ALGORITHM (TD)...............................................................................................................................65 
21.  EGRESS PACKET REMARKING ....................................................................................................................................65 

RTL8380M/RTL8382M/RTL8382L

Datasheet

10-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers v Track ID: Rev. 0.10

8.22. INGRESS AND EGRESS PORT MIRROR .........................................................................................................................65

8.22.1. Remote Mirror (RAPAN).................................................................................................................................66

8.23. MANAGEMENT INFORMATION BASE (MIB) ...............................................................................................................67

8.24. NIC AND CPU TAG FORWARDING .............................................................................................................................67

8.25. INDIRECT TABLE ACCESS...........................................................................................................................................68

8.26. EXTERNAL PHY REGISTER ACCESS...........................................................................................................................68

8.27. SWITCH INTERRUPT INDICATION................................................................................................................................68

9. CPU FUNCTION DESCRIPTION.................................................................................................................................68

9.1. MIPS-4KEC...............................................................................................................................................................68

9.2. SPI FLASH..................................................................................................................................................................69

9.3. SDRAM INTERFACE CONFIGURATION (RTL8380M/RTL8382M ONLY)..................................................................69

10. INTERFACE DESCRIPTIONS......................................................................................................................................70

10.1. QSGMII ....................................................................................................................................................................70

10.2. RSGMII.....................................................................................................................................................................70

10.3. SGMII .......................................................................................................................................................................71

10.4. DDR1 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................72

10.5. DDR2 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................73

10.6. DDR3 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................74

10.7. SPI FLASH INTERFACE ...............................................................................................................................................74

10.8. UART........................................................................................................................................................................75

10.9. EJTAG ......................................................................................................................................................................75

10.10. I2C MASTER FOR EEPROM ......................................................................................................................................76

10.11. I2C SLAVE INTERFACE...............................................................................................................................................76

10.12. SPI SLAVE INTERFACE ...............................................................................................................................................77

10.13. SERIAL LED...............................................................................................................................................................78

11. ELECTRICAL AC/DC CHARACTERISTICS.............................................................................................................80

11.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................80

11.2. OPERATING RANGE....................................................................................................................................................80

11.3. DC CHARACTERISTICS...............................................................................................................................................81

11.4. AC CHARACTERISTICS...............................................................................................................................................81

11.4.1. QSGMII Differential Transmitter Characteristics...........................................................................................81

11.4.2. QSGMII Differential Receiver Characteristics................................................................................................82

11.4.3. RSGMII Differential Transmitter Characteristics...........................................................................................84

11.4.4. RSGMII Differential Receiver Characteristics................................................................................................85

11.4.5. SGMII Differential Transmitter Characteristics..............................................................................................86

11.4.6. SGMII Differential Receiver Characteristics ..................................................................................................87

11.4.7. 1000Base-X/100Base-FX Differential Transmitter Characteristics................................................................88

11.4.8. 1000Base-X/100Base-FX Differential Receiver Characteristics.....................................................................89

11.4.9. DDR2 Characteristics .....................................................................................................................................90

11.4.10. DDR

Characteristics .....................................................................................................................................91

11.4.11. SPI Interface Characteristics...........................................................................................................................92

11.4.12. SMI (MDC/MDIO) Interface Characteristics..................................................................................................93

11.4.13. Serial Mode LED.............................................................................................................................................93

12. PACKAGE INFORMATION..........................................................................................................................................95

12.1. LQFP216-E-PAD (24*24MM)...................................................................................................................................95

13. ORDERING INFORMATION........................................................................................................................................97