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Vivado Design Suite
Tutorial
Designing IP Subsystems Using IP
Integrator
UG995 (v 2013.2) June 20, 2013
Notice of Disclaimer
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS
ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a
result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of
the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates
to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without
prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at
http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by
Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you
assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.
©Copyright 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, Vivado, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated
brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of
their respective owners...
Revision History
Date
Version
Revision
06/20/2013
2013.2
Minor editorial update.
06/19/2013
2013.2
New in this release.
Designing IP Subsystems Using IP Integrator www.xilinx.com 3
UG995 (v 2013.2) June 20, 2013
Table of Contents
Revision History........................................................................................................................................................... 2
Table of Contents ................................................................................................................................................................................. 3
Designing IP Subsystems .................................................................................................................................................................. 4
Introduction .................................................................................................................................................................. 4
Tutorial Design Description .................................................................................................................................... 4
Software Requirements ............................................................................................................................................ 4
Hardware Requirements .......................................................................................................................................... 5
Locating Tutorial Design Files ................................................................................................................................ 5
Lab 1: Designing IP Subsystems in IP Integrator ..................................................................................................................... 6
Step 1: Creating a Project ........................................................................................................................................ 6
Step 3: Creating External Connections ............................................................................................................ 13
Step 4: Customize IP ............................................................................................................................................... 18
Step 5: Running Connection Automation ...................................................................................................... 23
Step 6: Using the Address Editor ....................................................................................................................... 26
Step 7: Creating and Implementing the Top-Level Design ..................................................................... 28
Conclusion .................................................................................................................................................................. 33
Designing IP Subsystems Using IP Integrator www.xilinx.com 4
UG995 (v 2013.2) June 20, 2013
Designing IP Subsystems
Introduction
The Xilinx
®
Vivado
®
Design Suite IP integrator feature lets you create complex system designs
by instantiating and interconnecting IP cores from the Vivado IP catalog onto a design canvas.
You can create designs interactively through the IP integrator design canvas GUI, or
programmatically using a Tcl programming interface. You will typically construct designs at the
AXI interface level for greater productivity; but you may also manipulate designs at the port level
for more precise design control.
This tutorial walks you through the steps for building a basic IP subsystem design using the IP
Integrator tool. You will instantiate a few IP in the IP Integrator tool and then stitch them up to
create an IP sub-system design. While working on this tutorial, you will be introduced to the IP
Integrator GUI, run design rule checks (DRC) on your design, and then integrate the design in a
top-level design in the Vivado Design Suite. Finally, you will run synthesis and implementation
and generate bitstream on the design.
Tutorial Design Description
This tutorial is based on a simple non-processor based IP Integrator design. It contains a few
peripheral IP cores, and an AXI interconnect core, which connects to an external on-board
processor.
The design targets a xc7k325 Kintex device. A small design is used to allow the tutorial to be run
with minimal hardware requirements and to enable timely completion of the tutorial, as well as
to minimize the data size.
Software Requirements
This tutorial requires that the 2013.2 Vivado Design Suite software release or later is installed.
For installation instructions and information, see the Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
Hardware Requirements
Designing IP Subsystems Using IP Integrator www.xilinx.com 5
UG995 (v 2013.2) June 20, 2013
Hardware Requirements
The supported Operating Systems include Redhat 5.6 Linux 64 and 32 bit, and Windows 7, 64
and 32 bit.
Xilinx recommends a minimum of 2 GB of RAM when using the Vivado tool.
Locating Tutorial Design Files
This tutorial requires the standard Vivado Design Suite tutorial files, with the addition of a new
constraints file, top_ipi.xdc, which is available to download for use with the tutorial.
You can find the standard Vivado Design Suite tutorial files in the examples folder of the
Vivado tools installation, at the following location:
<Vivado_install_area>/Vivado/<version>/examples/Vivado_Tutorial.zip
You can extract the Vivado_Tutorial.zip file, at any time, to write the tutorial files to your
local directory, or to restore the files to their starting condition.
Extract the Vivado_Tutorial.zip file contents from the software installation into any 1.
write-accessible location.
The location of the extracted Vivado_Tutorial folder is referred to as the <Extract_Dir>
in this Tutorial.
Download the ug995-tutorial.zip file from the Xilinx website: 2.
http://www.xilinx.com/cgi-bin/docs/rdoc?v=2013.2;t=vivado+tutorials
Extract the ug995-tutorial.zip file into <Extract_Dir>/Vivado_Tutorial/Sources 3.
folder.
The new top_ipi.xdc file is added to the Sources folder. You are now ready to begin the
labs.
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