gtm-ip_specification_v3-1-5-1_boschGTM

GTM_IP

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Robert Bosch GmbH

Automotive Electronics (AE)

GTM-IP

Generic Timer Module

GTM-IP Specification

Revision: 3.1.5.1

(Released on 24.03.2016)

Automotive Electronics

GTM-IP Specification Revision 3.1.5.1

Robert Bosch GmbH iii 24.03.2016

Confidential

Table of Contents

1 Introduction .................................................................................................. 1

1.1 Overview ........................................................................................................ 1

1.2 Document Structure ....................................................................................... 2

1.2.1 Sub-module groups ..................................................................................... 2

2 GTM Architecture ......................................................................................... 3

2.1 Overview ........................................................................................................ 3

2.1.1 GTM Architecture Block Diagram ................................................................ 3

2.1.2 ARU Data Word Description ........................................................................ 5

2.1.3 GTM-IP signal multiplex .............................................................................. 7

2.1.4 TIM auxiliary input multiplexing ................................................................... 7

2.1.5 TIM external capture forwarding to TOM and ATOM................................... 8

2.1.6 TIM to MCS signal forwarding ..................................................................... 9

2.2 GTM-IP Interfaces .........................................................................................10

2.2.1 GTM-IP Generic Bus Interface (AEI) ..........................................................11

2.2.2 GTM-IP Multi-master and multitasking support ..........................................12

2.3 ARU Routing Concept ...................................................................................12

2.3.1 Principle of data routing using ARU ............................................................13

2.3.2 ARU source and destination address count per instance ...........................14

2.3.3 ARU Round Trip Time ................................................................................15

2.3.4 ARU Blocking Mechanism ..........................................................................15

2.4 GTM-IP Clock and Time Base Management (CTBM) ...................................16

2.4.1 GTM-IP Clock and time base management architecture ............................16

2.4.2 Cyclic Event Compare ................................................................................17

2.5 GTM-IP Interrupt Concept .............................................................................18

2.5.1 Level interrupt mode ...................................................................................21

2.5.2 Pulse interrupt mode ..................................................................................23

2.5.3 Pulse-notify interrupt mode ........................................................................24

2.5.4 Single-pulse interrupt mode .......................................................................25

2.5.5 GTM-IP Interrupt concentration method .....................................................27

2.6 GTM-IP Software Debugger Support ............................................................27

2.6.1 Register behavior in case of Software Debugger accesses .......................27

2.7 GTM-IP Programming conventions ...............................................................28

2.8 GTM-IP TOP-Level Configuration Register Overview ...................................28

2.8.1 GTM-IP TOP-Level Configuration Register Overview Table ......................29

2.9 GTM TOP-Level Configuration Registers Description ...................................29

2.9.1 Register GTM_REV ....................................................................................29

2.9.2 Register GTM_RST ....................................................................................30

2.9.3 Register GTM_CTRL ..................................................................................31

2.9.4 Register GTM_AEI_ADDR_XPT ................................................................32

2.9.5 Register GTM_AEI_STA_XPT ...................................................................32

2.9.6 Register GTM_IRQ_NOTIFY .....................................................................33

2.9.7 Register GTM_IRQ_EN ..............................................................................35

2.9.8 Register GTM_IRQ_FORCINT ...................................................................37

Automotive Electronics

GTM-IP Specification Revision 3.1.5.1

Robert Bosch GmbH iv 24.03.2016

Confidential

2.9.9 Register GTM_IRQ_MODE ........................................................................38

2.9.10 Register GTM_BRIDGE_MODE.................................................................39

2.9.11 Register GTM_BRIDGE_PTR1 ..................................................................41

2.9.12 Register GTM_BRIDGE_PTR2 ..................................................................42

2.9.13 Register GTM_MCS_AEM_DIS .................................................................43

2.9.14 Register GTM_EIRQ_EN ...........................................................................44

2.9.15 Register GTM_CLS_CLK_CFG..................................................................45

2.9.16 Register GTM_CFG ...................................................................................49

3 Advanced Routing Unit (ARU) ...................................................................50

3.1 Overview .......................................................................................................50

3.2 Special Data Sources ...................................................................................50

3.3 ARU Access via AEI .....................................................................................51

3.3.1 Default ARU Access ...................................................................................51

3.3.2 Debug Access ............................................................................................52

3.4 ARU dynamic routing ....................................................................................53

3.4.1 Dynamic routing - CPU controlled ..............................................................53

3.4.2 Dynamic routing - ARU controlled ..............................................................56

3.5 ARU Interrupt Signals ...................................................................................56

3.5.1 ARU Interrupt Signals Table .......................................................................57

3.6 ARU Configuration Register Overview ..........................................................57

3.6.1 ARU Configuration Register Overview Table .............................................57

3.7 ARU Configuration Register Description .......................................................58

3.7.1 Register ARU_ACCESS .............................................................................58

3.7.2 Register ARU_DATA_H .............................................................................59

3.7.3 Register ARU_DATA_L ..............................................................................60

3.7.4 Register ARU_DBG_ACCESS0 .................................................................61

3.7.5 Register ARU_DBG_DATA0_H .................................................................61

3.7.6 Register ARU_DBG_DATA0_L ..................................................................62

3.7.7 Register ARU_DBG_ACCESS1 .................................................................62

3.7.8 Register ARU_DBG_DATA1_H .................................................................63

3.7.9 Register ARU_DBG_DATA1_L ..................................................................64

3.7.10 Register ARU_IRQ_NOTIFY ......................................................................64

3.7.11 Register ARU_IRQ_EN ..............................................................................65

3.7.12 Register ARU_IRQ_FORCINT ...................................................................66

3.7.13 Register ARU_IRQ_MODE ........................................................................66

3.7.14 Register ARU_CADDR_END .....................................................................67

3.7.15 Register ARU_CADDR ...............................................................................68

3.7.16 Register ARU_CTRL ..................................................................................68

3.7.17 Register ARU_[z]_DYN_CTRL (z:0...1) ......................................................69

3.7.18 Register ARU_[z]_DYN_RDADDR (z:0...1) ................................................70

3.7.19 Register ARU_[z]_DYN_ROUTE_LOW (z:0...1) ........................................71

3.7.20 Register ARU_[z]_DYN_ROUTE_HIGH (z:0...1)........................................71

3.7.21 Register ARU_[z]_DYN_ROUTE_SR_LOW (z:0...1) .................................72

3.7.22 Register ARU_[z]_DYN_ROUTE_SR_HIGH (z:0...1) .................................72

4 Broadcast Module (BRC) ............................................................................74

4.1 Overview .......................................................................................................74

4.2 BRC Configuration ........................................................................................74

Automotive Electronics

GTM-IP Specification Revision 3.1.5.1

Robert Bosch GmbH v 24.03.2016

Confidential

4.3 BRC Interrupt Signals ...................................................................................76

4.4 BRC Configuration Register Overview ..........................................................76

4.4.1 BRC Configuration Register Overview Table .............................................76

4.5 BRC Configuration Register Description .......................................................77

4.5.1 Register BRC_SRC_[z]_ADDR (z:0...11) ...................................................77

4.5.2 Register BRC_SRC_[z]_DEST (z:0...11) ...................................................77

4.5.3 Register BRC_IRQ_NOTIFY ......................................................................79

4.5.4 Register BRC_IRQ_EN ..............................................................................80

4.5.5 Register BRC_IRQ_FORCINT ...................................................................81

4.5.6 Register BRC_IRQ_MODE ........................................................................82

4.5.7 Register BRC_EIRQ_EN ............................................................................82

4.5.8 Register BRC_RST ....................................................................................83

5 First In First Out Module (FIFO) .................................................................84

5.1 Overview .......................................................................................................84

5.2 Operation Modes ..........................................................................................85

5.2.1 FIFO Operation Mode ................................................................................85

5.2.2 Ring Buffer Operation Mode .......................................................................85

5.2.3 DMA Hysteresis Mode ................................................................................86

5.3 FIFO Interrupt Signals ...................................................................................86

5.4 FIFO Configuration Register Overview .........................................................86

5.5 FIFO Configuration Registers Description ....................................................87

5.5.1 Register FIFO[i]_CH[z]_CTRL (z:0...7) .......................................................87

5.5.2 Register FIFO[i]_CH[z]_END_ADDR (z:0...7) ............................................88

5.5.3 Register FIFO[i]_CH[z]_START_ADDR (z:0...7) ........................................89

5.5.4 Register FIFO[i]_CH[z]_UPPER_WM (z:0...7) ...........................................89

5.5.5 Register FIFO[i]_CH[z]_LOWER_WM (z:0...7)...........................................90

5.5.6 Register FIFO[i]_CH[z]_STATUS (z:0...7) ..................................................91

5.5.7 Register FIFO[i]_CH[z]_FILL_LEVEL (z:0...7) ............................................91

5.5.8 Register FIFO[i]_CH[z]_WR_PTR (z:0...7) .................................................92

5.5.9 Register FIFO[i]_CH[z]_RD_PTR (z:0...7) ..................................................93

5.5.10 Register FIFO[i]_CH[z]_IRQ_NOTIFY (z:0...7)...........................................93

5.5.11 Register FIFO[i]_CH[z]_IRQ_EN (z:0...7) ...................................................94

5.5.12 Register FIFO[i]_CH[z]_IRQ_FORCINT (z:0...7) ........................................94

5.5.13 Register FIFO[i]_CH[z]_IRQ_MODE (z:0...7) .............................................95

5.5.14 Register FIFO[i]_CH[z]_EIRQ_EN (z:0...7) ................................................96

6 AEI to FIFO Data Interface (AFD) ...............................................................97

6.1 Overview .......................................................................................................97

6.2 AFD Register overview .................................................................................97

6.3 AFD Register description ..............................................................................97

6.3.1 Register AFD[i]_CH[z]_BUF_ACC (z:0...7) ................................................97

7 FIFO to ARU Unit (F2A) ..............................................................................99

7.1 Overview .......................................................................................................99

7.2 Transfer modes .............................................................................................99

7.2.1 Data transfer of both ARU words between ARU and FIFO ......................100

7.3 Internal buffer mode ....................................................................................100

7.3.1 Reconfiguration of F2A stream 4 to FIFO channel 0 ................................101

7.4 F2A Configuration Register Overview .........................................................101

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