ADV7123数据手册

ADV7123

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CMOS, 330 MHz

Triple 10-Bit High Speed Video DAC

ADV7123

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

330 MSPS throughput rate

Triple 10-bit digital-to-analog converters (DACs)

SFDR

−70 dB at f

CLK

= 50 MHz; f

OUT

= 1 MHz

−53 dB at f

CLK

= 140 MHz; f

OUT

= 40 MHz

RS-343A-/RS-170-compatible output

Complementary outputs

DAC output current range: 2.0 mA to 26.5 mA

TTL-compatible inputs

Internal reference (1.235 V)

Single-supply 5 V/3.3 V operation

48-lead LQFP package

Low power dissipation (30 mW minimum @ 3 V)

Low power standby mode (6 mW typical @ 3 V)

Industrial temperature range (−40°C to +85°C)

Pb-free (lead-free) package

APPLICATIONS

Digital video systems (1600 × 1200 @ 100 Hz)

High resolution color graphics

Digital radio modulation

Image processing

Instrumentation

Video signal reconstruction

FUNCTIONAL BLOCK DIAGRAM

DATA

DAC

BLANK

SYNC

R9 TO R0

G9 TO G0

B9 TO B0

PSAVE

CLOCK

DAC

ADV7123

DATA

BLANK AND

SYNC LOGIC

POWER-DOWN

MODE

VOLTAGE

REFERENCE

CIRCUIT

IOR

IOG

IOB

REF

SET

COMPGND

IOB

00215-001

Figure 1.

GENERAL DESCRIPTION

The ADV7123 (ADV®) is a triple high speed, digital-to-analog

converter on a single monolithic chip. It consists of three high

speed, 10-bit, video DACs with complementary outputs, a

standard TTL input interface, and a high impedance, analog

output current source.

The ADV7123 has three separate 10-bit-wide input ports. A

single 5 V/3.3 V power supply and clock are all that are required

to make the part functional. The ADV7123 has additional video

control signals, composite

SYNC

and

BLANK

The ADV7123 also has a power save mode.

The ADV7123 is fabricated in a 5 V CMOS process. Its

monolithic CMOS construction ensures greater functionality

with lower power dissipation. The ADV7123 is available in a

48-lead LQFP package.

PRODUCT HIGHLIGHTS

1. 330 MSPS throughput.

2. Guaranteed monotonic to 10 bits.

3. Compatible with a wide variety of high resolution color

graphics systems, including RS-343A and RS-170.

ADV is a registered trademark of Analog Devices, Inc.

ADV7123

Rev. D | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

5 V Specifications ......................................................................... 3

3.3 V Specifications ...................................................................... 4

5 V Dynamic Specifications ........................................................ 5

3.3 V Dynamic Specifications ..................................................... 6

5 V Timing Specifications ........................................................... 7

3.3 V Timing Specifications ........................................................ 8

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

5 V Typical Performance Characteristics ................................ 12

3 V Typical Performance Characteristics ................................ 14

Terminology .................................................................................... 16

Circuit Description and Operation .............................................. 17

Digital Inputs .............................................................................. 17

Clock Input .................................................................................. 17

Video Synchronization and Control ........................................ 18

Reference Input ........................................................................... 18

DACs ............................................................................................ 18

Analog Outputs .......................................................................... 18

Gray Scale Operation ................................................................. 19

Video Output Buffers ................................................................. 19

PCB Layout Considerations ...................................................... 19

Digital Signal Interconnect ....................................................... 19

Analog Signal Interconnect....................................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

REVISION HISTORY

7/10—Rev. C to Rev. D

Changes to Figure 2 .......................................................................... 9

Changes to Figure 22 and Figure 23 ............................................. 17

Changes to Table 9 .......................................................................... 18

3/09—Rev. B to Rev. C

Updated Format .................................................................. Universal

Changes to Features Section............................................................ 1

Changes to Table 5 ............................................................................ 7

Changes to Table 6 ............................................................................ 8

Changes to Table 8 .......................................................................... 10

Changed f

CLOCK

to f

CLK

..................................................................... 12

Changes to Figure 6, Figure 7, and Figure 8................................ 12

Changes to Figure 13 and Figure 17 ............................................. 14

Deleted Ground Planes Section, Power Planes Section, and

Supply Decoupling Section ........................................................... 15

Changes to Figure 23 ...................................................................... 17

Changes to Table 9, Analog Outputs Section, Figure 24, and

Figure 25 .......................................................................................... 18

Changes to Video Output Buffers Section and PCB Layout

Considerations Section .................................................................. 19

Changes to Analog Signal Interconnect Section and

Figure 28 .......................................................................................... 20

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

10/02—Rev. A to Rev. B

Change in Title ................................................................................... 1

Change to Feature .............................................................................. 1

Change to Product Highlights ......................................................... 1

Change Specifications ....................................................................... 3

Change to Pin Function Descriptions ......................................... 10

Change to Reference Input section .............................................. 18

Change to Figure 28 ....................................................................... 22

Updated Outline Dimensions ....................................................... 23

Change to Ordering Guide ............................................................ 23

ADV7123

Rev. D | Page 3 of 24

SPECIFICATIONS

5 V SPECIFICATIONS

= 5 V ± 5%, V

REF

= 1.235 V, R

SET

= 560 Ω, C

= 10 pF. All specifications T

MIN

to T

MAX

unless otherwise noted, T

J MAX

= 110°C.

Table 1.

Parameter Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits

Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB

Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic

DIGITAL AND CONTROL INPUTS

Input High Voltage, V

2 V

Input Low Voltage, V

0.8 V

Input Current, I

−1 +1 μA V

= 0.0 V or V

PSAVE Pull-Up Current

20 μA

Input Capacitance, C

10 pF

ANALOG OUTPUTS

Output Current 2.0 26.5 mA

Green DAC, SYNC

= high

2.0 18.5 mA

RGB DAC, SYNC

= low

DAC-to-DAC Matching 1.0 5 %

Output Compliance Range, V

0 1.4 V

Output Impedance, R

OUT

100 kΩ

Output Capacitance, C

OUT

10 pF I

OUT

= 0 mA

Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V

Gain Error

−5.0 +5.0 % FSR FSR = 17.62 mA

VOLTAGE REFERENCE, EXTERNAL AND

INTERNAL

Reference Range, V

REF

1.12 1.235 1.35 V

POWER DISSIPATION

Digital Supply Current

3.4 9 mA f

CLK

= 50 MHz

10.5 15 mA f

CLK

= 140 MHz

18 25 mA f

CLK

= 240 MHz

Analog Supply Current 67 72 mA R

SET

= 560 Ω

8 mA R

SET

= 4933 Ω

Standby Supply Current

2.1 5.0 mA

PSAVE

= low, digital, and control inputs at V

Power Supply Rejection Ratio 0.1 0.5 %/%

Temperature range T

MIN

to T

MAX

: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.

Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = V

REF

SET

× K × (0x3FFH) and K = 7.9896.

Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and V

These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.

ADV7123

Rev. D | Page 4 of 24

3.3 V SPECIFICATIONS

= 3.0 V to 3.6 V, V

REF

= 1.235 V, R

SET

= 560 Ω, C

= 10 pF. All specifications T

MIN

to T

MAX

unless otherwise noted, T

J MAX

= 110°C.

Table 2.

Parameter

Min Typ Max Unit Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits R

SET

= 680 Ω

Integral Nonlinearity (BSL) −1 +0.5 +1 LSB R

SET

= 680 Ω

Differential Nonlinearity −1 +0.25 +1 LSB R

SET

= 680 Ω

DIGITAL AND CONTROL INPUTS

Input High Voltage, V

2.0 V

Input Low Voltage, V

0.8 V

Input Current, I

−1 +1 μA V

= 0.0 V or V

PSAVE Pull-Up Current

20 μA

Input Capacitance, C

10 pF

ANALOG OUTPUTS

Output Current 2.0 26.5 mA

Green DAC, SYNC

= high

2.0 18.5 mA

RGB DAC, SYNC

= low

DAC-to-DAC Matching 1.0 %

Output Compliance Range, V

0 1.4 V

Output Impedance, R

OUT

70 kΩ

Output Capacitance, C

OUT

10 pF

Offset Error 0 0 % FSR Tested with DAC output = 0 V

Gain Error

0 % FSR FSR = 17.62 mA

VOLTAGE REFERENCE, EXTERNAL

Reference Range, V

REF

1.12 1.235 1.35 V

VOLTAGE REFERENCE, INTERNAL

Voltage Reference, V

REF

1.235 V

POWER DISSIPATION

Digital Supply Current

2.2 5.0 mA f

CLK

= 50 MHz

6.5 12.0 mA f

CLK

= 140 MHz

11 15 mA f

CLK

= 240 MHz

16 mA f

CLK

= 330 MHz

Analog Supply Current 67 72 mA R

SET

= 560 Ω

8 mA R

SET

= 4933 Ω

Standby Supply Current 2.1 5.0 mA

PSAVE

= low, digital, and control inputs at V

Power Supply Rejection Ratio 0.1 0.5 %/%

Temperature range T

MIN

to T

MAX

: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.

These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.

Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = V

REF

SET

× K × (0x3FFH) and K = 7.9896.

Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and V

ADV7123

Rev. D | Page 5 of 24

5 V DYNAMIC SPECIFICATIONS

= 5 V ± 5%,

REF

= 1.235 V, R

SET

= 560 Ω, C

= 10 pF. All specifications are T

= 25°C, unless otherwise noted, T

J MAX

= 110°C.

Table 3.

Parameter

Min Typ Max Unit

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

Single-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz 67 dBc

CLK

= 50 MHz; f

OUT

= 2.51 MHz 67 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz 63 dBc

CLK

= 50 MHz; f

OUT

= 20.2 MHz 55 dBc

CLK

= 100 MHz; f

OUT

= 2.51 MHz 62 dBc

CLK

= 100 MHz; f

OUT

= 5.04 MHz 60 dBc

CLK

= 100 MHz; f

OUT

= 20.2 MHz 54 dBc

CLK

= 100 MHz; f

OUT

= 40.4 MHz 48 dBc

CLK

= 140 MHz; f

OUT

= 2.51 MHz 57 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz 58 dBc

CLK

= 140 MHz; f

OUT

= 20.2 MHz 52 dBc

CLK

= 140 MHz; f

OUT

= 40.4 MHz 41 dBc

Double-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz 70 dBc

CLK

= 50 MHz; f

OUT

= 2.51 MHz 70 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz 65 dBc

CLK

= 50 MHz; f

OUT

= 20.2 MHz 54 dBc

CLK

= 100 MHz; f

OUT

= 2.51 MHz 67 dBc

CLK

= 100 MHz; f

OUT

= 5.04 MHz 63 dBc

CLK

= 100 MHz; f

OUT

= 20.2 MHz 58 dBc

CLK

= 100 MHz; f

OUT

= 40.4 MHz 52 dBc

CLK

= 140 MHz; f

OUT

= 2.51 MHz 62 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz 61 dBc

CLK

= 140 MHz; f

OUT

= 20.2 MHz 55 dBc

CLK

= 140 MHz; f

OUT

= 40.4 MHz 53 dBc

Spurious-Free Dynamic Range Within a Window

Single-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz; 1 MHz Span 77 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz; 2 MHz Span 73 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz; 4 MHz Span 64 dBc

Double-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz; 1 MHz Span 74 dBc

CLK

= 50 MHz; f

OUT

= 5.00 MHz; 2 MHz Span 73 dBc

CLK

= 140 MHz; f

OUT

= 5.00 MHz; 4 MHz Span 60 dBc

Total Harmonic Distortion

CLK

= 50 MHz; f

OUT

= 1.00 MHz

= 25°C 66 dBc

MIN

to T

MAX

65 dBc

CLK

= 50 MHz; f

OUT

= 2.00 MHz 64 dBc

CLK

= 100 MHz; f

OUT

= 2.00 MHz 63 dBc

CLK

= 140 MHz; f

OUT

= 2.00 MHz 55 dBc

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