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Stratus High Level Synthesis User Guide
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The first high-level synthesis platform for use across your entire SoC design, Stratus High-Level Synthesis (HLS) delivers up to 10X better productivity than traditional RTL design. Based on more than 14 years of production HLS deployment, the Stratus tool lets you quickly design and verify high-quality RTL implementations from abstract SystemC, C, or C++ models.
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Stratus High-Level Synthesis User Guide
Product Version 17.1
May 2017
© 2017 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America.
Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA.
Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or
registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and
are used with permission.
Trademarks : Trademarks and service marks of Cadence Design Systems, Inc. contained in this
document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence's
trademarks, contact the corporate legal department at the address shown above or call
800.862.4522. All other trademarks are the property of their respective holders.
Restricted Permission: This publication is protected by copyright law and international treaties
and contains trade secrets and proprietary information owned by Cadence. Unauthorized
reproduction or distribution of this publication, or any portion of it, may result in civil and criminal
penalties. Except as specified in this permission statement, this publication may not be copied,
reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without
prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this
statement grants Cadence customers permission to print one (1) hard copy of this publication
subject to the following conditions:
1. The publication may be used only in accordance with a written agreement between Cadence
and its customer.
2. The publication may not be modified in any way.
3. Any authorized copy of the publication or portion thereof must include all original copyright,
trademark, and other proprietary notices and this permission statement.
4. The information contained in this document cannot be used in the development of like
products or software, whether for internal or external use, and shall not be used for the benefit
of any other party, whether or not for consideration.
Disclaimer: Information in this publication is subject to change without notice and does not
represent a commitment on the part of Cadence. Except as may be explicitly set forth in such
agreement, Cadence does not make, and expressly disclaims, any representations or warranties as
to the completeness, accuracy or usefulness of the information contained in this document.
Cadence does not warrant that use of such information will not infringe any third party rights, nor
does Cadence assume any liability for damages or costs of any kind that may result from use of
such information.
Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as
set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.
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Contents
1
Preface
About this Document
Other Resources
Using the Documentation
Typographical Conventions
Customer Support
Cases
Using Cadence Online Support
Cadence Online Support
2
Stratus High-Level Synthesis Overview
What is Behavioral Synthesis?
The Stratus HLS Approach
Integrations
Simulation
Logic Synthesis
Debugging
Emacs Editor in Stratus IDE
Schematic and Waveform Viewing
Power Analysis
Equivalence Checking
Code Analysis
3
Stratus High-Level Synthesis Flow
Stratus HLS Design Flow
Stepwise Design Process
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Assembling the Files for Your Project
Overview
File Descriptions
5
Preparing Your Design for Stratus HLS
Preparing Your Design
Representing the Design as an SC_MODULE
Module Hierarchies
Specifying Reset Behavior
Specifying Multi-Cycle Initialization Behavior
Specifying the Main Loop
SC_MODULE Example
Describing I/O Protocol
Describing Protocol-Accurate Behavior with the HLS_DEFINE_PROTOCOL Directive
Using Handshaking Protocols
Using Protocol Blocks to Register Inputs
Setting an Input Delay
Declaring Inputs as Stable to Avoid any Registering
Driving Ports and Signals from Multiple Threads
Accessing External Memories in Free-Scheduled Regions
Using struct and class Data Types in Your Design
Using Virtual Functions
Using Pointers
Example of Design Code Transformation
Basic C++ Algorithm
C++ Algorithm Using SystemC Constructs
Behavioral Design Ready for Stratus HLS
Specifying Cycle-Accurate Designs
Partitioning of a Design into Smaller Regions
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Partitioning Using dpopt_region
Partitioning Using schedule_region
Partitioning Using Explicit Partitioning
6
Controlling Micro-Architecture
Synthesis Control Attributes
Synthesis Directives and Synthesis Tcl Commands
Specifying Synthesis Tcl Commands
The Project Object Model
Using the CDFG Viewer
Graph Displays
Using the Object Tree Browser
7
I/O Scheduling Contexts
Introduction
Specifying an FSM in a HLS_DEFINE_PROTOCOL Block
Implicit FSM
Resets
HLS_DEFINE_PROTOCOL Example
Conditional Branches
Loops
8
Preparing Your Testbench and SystemC Module Hierarchy
Preparing Your Testbench
Initializing and Terminating the Simulation
Organizing the sc_main Function with ESC Functions
Instantiating Design Modules Using Stratus HLS-Wrappers
Instantiating Hierarchies of Design Modules
Using C++ Templates with hls_modules
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