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首页复杂百万门集成芯片的DFT测试方案.pdf
复杂百万门集成芯片的DFT测试方案.pdf
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更新于2023-03-16
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本文介绍了复杂的百万门ASIC芯片Lugia中几个DFT相关问题的解决方案。 这些问题包括:1)用于测试的有限封装引脚; 2)扫描链穿过电源平面边界导致的功率泄漏; 3)DFT模拟样式选择,以节省模拟时间
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A DFT Experience in a Complex Million Gate Design
Na Zou
Jincheng Li
ALi Corporation, Shanghai, China
Anne_Zou@ali.com.tw
Euphoria_Lee@ali.com.tw
ABSTRACT
This paper presents the solutions to several DFT related issues in our complex million-gate
ASIC chip, Lugia. These issues include: 1) Limited package pins for test; 2) Power-leakage
resulting from scan chains crossing power plane boundaries; 3) DFT simulation style
selection to save simulation time.
SNUG China 2003 2 A DFT Experience in a Complex Million Gate Design
1. DFT challenges and DFT goal of Lugia
Lugia, a mass-produced ASIC product of ALi Corp., offers computer users several attractive
functions in a single chip with high integration efficiency. It is a million-gate ASIC which
integrates an IEEE1394 link layer chip, four USB 2.0/1.1 Host Controllers for a total of 6
USB ports, a Secure Digital (SD) Host Controller and a Memory Stick (MS) Host Controller.
(http://www.ali.com.tw/eng/product/peripheral/m5271.htm)
We selected full scan as our DFT methodology for Lugia. The goal of DFT is to meet fault
coverage up to 95% with, at the same time, low cost of total test time. This is not so easy for
a million-gate design with multiple power domains and limited package pins for test.
The first problem is pin limited. There is no free pin left on the chip that can be used as pure
test IO pins, so we have to share the test IO pins with the functional ones. However, 56 of
Lugia’s IO pins among the total 160 pins are used as power pins or other pins that cannot be
shared with the test. So only 104 pins left can be used as both normal function pins and test
IO pins. If we can make use of them all as test IO pins, we will have 52 scan chains on the
chip. On the other hand, Lugia contains around 37K flip-flops, so there will be about 710
flip-flops in each scan chain on average. If we can not fully make use of all possible pins for
test IO, for example if we only use the IO pins for 50 scan chains, then there will be about
740 flip-flops in every scan, so test time will be increased by about 4%, which means more
product cost. So we have to try our best to use all 52 chains for our design. Besides, we must
balance the number of flip-flops in each scan chain since that the longest scan chain
determines test time, and finally the test cost.
However, auto-generated control logic from DFT Compiler cannot do this perfectly. We
write a PAD Control block in RTL manually to organize the control logic at very beginning
of our DFT process.
The second issue is derived from the two power domains in Lugia, whose block diagram is
shown in Figure 1. The top design name is PRM5271. It can be divided into three parts:
TM5271: Consists USB, IEEE1394, MS, SD, PCI 2.3 Interface Control, Hardware
Setting, Interrupt Control and other control blocks.
PAD: Contains PADs for the ASIC.
PAD_CTRL: the PAD Control block we just mentioned.
SNUG China 2003 3 A DFT Experience in a Complex Million Gate Design
Figure 1. Structure of Lugia in Two Power Planes
Lugia can be divided into two power planes: main power plane and resume power plane.
Shadow in Figure 1 represents resume power plane. Most of cells belong to main power
plane, where power will be shut down in suspend state. Resume power plan will run all the
time and never be shut down. Logic in resume power plane is able to wake up whole system
out of suspend state.
We have to stitch each scan chain independently in each power plane to avoid the current
leakage circuits on scan chains. In other words, the scan chains should not cross the power
planes in our design. If for some reasons, the scan chain needs to go across the power planes,
extra logic should be added to cut off the current leakage. Apparently, this cannot be done
using DFT Compiler scan chain insertion automatically. You may find the details in section
4.
The final issue is the slow speed of the post-layout simulation with ATPG vectors due to the
huge gate-count of Lugia. We will address this problem in section 5.2.
All above issues must be solved so we can meet our DFT goal of up to 95% fault coverage
with low cost.
2. DFT steps in the whole design flow
The whole design flow of Lugia is shown in Figure 2. We ignore some contents that are not
so important for DFT.
IP RTLQA (RTL Quality Assessment) evaluates the RTL quality of the IPs. One of the
important metric is the DFT check. This will make sure that the IPs are testable before they
are integrated into the chip.
We use DFT Compiler RTL TestDRC to check for test design rule when full chip RTL is
available. This ensures the success of 1-pass synthesis in the next step.
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