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Veloce User Guide.pdf
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Veloce User Guide
Release v20.0.1
Document Revision 5.0
Unpublished work. © Siemens 2020
This document contains information that is confidential and proprietary to Mentor Graphics Corporation, Siemens
Industry Software Inc., or their affiliates (collectively, "Siemens"). The original recipient of this document may
duplicate this document in whole or in part for internal business purposes only, provided that this entire notice
appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort
to prevent the unauthorized use and distribution of the confidential and proprietary information.
This document is for information and instruction purposes. Siemens reserves the right to make changes in
specifications and other information contained in this publication without prior notice, and the reader should, in all
cases, consult Siemens to determine whether any changes have been made.
The terms and conditions governing the sale and licensing of Siemens products are set forth in written agreements
between Siemens and its customers. End User License Agreement — You can print a copy of the End User
License Agreement from: mentor.com/eula.
No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give
rise to any liability of Siemens whatsoever.
SIEMENS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
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SIEMENS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, CONSEQUENTIAL OR
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Veloce User Guide, v20.0.1
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Revision History ISO-26262
Author: In-house procedures and working practices require multiple authors for documents. All
associated authors for each topic within this document are tracked within the Mentor Graphics
Technical Publication’s source. For specific topic authors, contact Mentor Graphics Technical
Publication department.
Revision History: Released documents maintain a revision history of up to four revisions. For
earlier revision history, refer to earlier releases of documentation which are available on http://
support.mentor.com.
Revision Changes Status/
Date
5.0 Modifications to improve the readability and comprehension of
the content. Approved by Farshad Dailami.
All technical enhancements, changes, and fixes listed in the
Veloce Release Notes for this product are reflected in this
document. Approved by C.P. Jain.
Released
April 2020
4.3 Modifications to improve the readability and comprehension of
the content. Approved by Farshad Dailami.
All technical enhancements, changes, and fixes listed in the
Veloce Release Notes for this product are reflected in this
document. Approved by C.P. Jain.
Released
November
2019
4.2 Modifications to improve the readability and comprehension of
the content. Approved by Farshad Dailami.
All technical enhancements, changes, and fixes listed in the
Veloce Release Notes for this product are reflected in this
document. Approved by C.P. Jain.
Released
August
2019
4.1 Modifications to improve the readability and comprehension of
the content. Approved by Farshad Dailami.
All technical enhancements, changes, and fixes listed in the
Veloce Release Notes for this product are reflected in this
document. Approved by C.P. Jain.
Released
June 2019
Veloce User Guide, v20.0.1
4
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Veloce User Guide, v20.0.1
5
Table of Contents
Revision History ISO-26262
Chapter 1
Veloce Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Veloce Hardware Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Veloce Emulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Veloce Use Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Chapter 2
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Setting up Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Environment Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Setting Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Setting up Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Creating a Design Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Preparing HDL and HVL Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Setting up and Mapping Analysis Libraries Before Analysis. . . . . . . . . . . . . . . . . . . . . . . 29
Using a Libmap File for Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Creating a veloce.config File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chapter 3
Compiling Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Analyzing RTL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Compiling for Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Improving Emulation Performance with velsyn Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Improving Compile Time With Template Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Compiling HVL Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Compiling C/C++/SystemC HVL Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Automated C Compile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Compiling for Custom User Executable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Compiling for Dynamic Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Compiling with GCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Instantiating Buried SystemC Modules in an RTL Design . . . . . . . . . . . . . . . . . . . . . . . . 58
Specifying Clocks and IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Exporting a Compiled Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Importing a Gate-Level Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DesignWare Integration with RTLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Verilog DesignWare Component Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Verilog DesignWare Datapath Function Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
VHDL DesignWare Component Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
VHDL DesignWare Function Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Veloce Supported DesignWare Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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